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https://github.com/brain-hackers/u-boot-brain
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e87f3b308c
The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
119 lines
2.1 KiB
C
119 lines
2.1 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_NS_ACCESS_H_
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#define __FSL_NS_ACCESS_H_
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enum csu_cslx_access {
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CSU_NS_SUP_R = 0x08,
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CSU_NS_SUP_W = 0x80,
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CSU_NS_SUP_RW = 0x88,
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CSU_NS_USER_R = 0x04,
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CSU_NS_USER_W = 0x40,
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CSU_NS_USER_RW = 0x44,
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CSU_S_SUP_R = 0x02,
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CSU_S_SUP_W = 0x20,
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CSU_S_SUP_RW = 0x22,
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CSU_S_USER_R = 0x01,
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CSU_S_USER_W = 0x10,
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CSU_S_USER_RW = 0x11,
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CSU_ALL_RW = 0xff,
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};
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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CSU_CSLX_PCIE1_IO,
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CSU_CSLX_MG2TPR_IP,
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CSU_CSLX_IFC_MEM,
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CSU_CSLX_OCRAM,
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CSU_CSLX_GIC,
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CSU_CSLX_PCIE1,
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CSU_CSLX_OCRAM2,
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CSU_CSLX_QSPI_MEM,
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CSU_CSLX_PCIE2,
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CSU_CSLX_SATA,
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CSU_CSLX_USB3,
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CSU_CSLX_SERDES = 32,
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CSU_CSLX_QDMA,
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CSU_CSLX_LPUART2,
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CSU_CSLX_LPUART1,
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CSU_CSLX_LPUART4,
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CSU_CSLX_LPUART3,
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CSU_CSLX_LPUART6,
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CSU_CSLX_LPUART5,
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CSU_CSLX_DSPI2 = 40,
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CSU_CSLX_DSPI1,
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CSU_CSLX_QSPI,
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CSU_CSLX_ESDHC,
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CSU_CSLX_2D_ACE,
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CSU_CSLX_IFC,
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CSU_CSLX_I2C1,
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CSU_CSLX_USB2,
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CSU_CSLX_I2C3,
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CSU_CSLX_I2C2,
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CSU_CSLX_DUART2 = 50,
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CSU_CSLX_DUART1,
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CSU_CSLX_WDT2,
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CSU_CSLX_WDT1,
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CSU_CSLX_EDMA,
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CSU_CSLX_SYS_CNT,
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CSU_CSLX_DMA_MUX2,
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CSU_CSLX_DMA_MUX1,
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CSU_CSLX_DDR,
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CSU_CSLX_QUICC,
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CSU_CSLX_DCFG_CCU_RCPM = 60,
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CSU_CSLX_SECURE_BOOTROM,
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CSU_CSLX_SFP,
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CSU_CSLX_TMU,
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CSU_CSLX_SECURE_MONITOR,
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CSU_CSLX_RESERVED0,
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CSU_CSLX_ETSEC1,
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CSU_CSLX_SEC5_5,
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CSU_CSLX_ETSEC3,
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CSU_CSLX_ETSEC2,
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CSU_CSLX_GPIO2 = 70,
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CSU_CSLX_GPIO1,
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CSU_CSLX_GPIO4,
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CSU_CSLX_GPIO3,
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CSU_CSLX_PLATFORM_CONT,
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CSU_CSLX_CSU,
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CSU_CSLX_ASRC,
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CSU_CSLX_SPDIF,
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CSU_CSLX_FLEXCAN2,
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CSU_CSLX_FLEXCAN1,
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CSU_CSLX_FLEXCAN4 = 80,
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CSU_CSLX_FLEXCAN3,
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CSU_CSLX_SAI2,
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CSU_CSLX_SAI1,
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CSU_CSLX_SAI4,
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CSU_CSLX_SAI3,
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CSU_CSLX_FTM2,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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CSU_CSLX_FTM3,
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CSU_CSLX_FTM6 = 90,
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CSU_CSLX_FTM5,
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CSU_CSLX_FTM8,
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CSU_CSLX_FTM7,
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CSU_CSLX_COP_DCSR,
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CSU_CSLX_EPU,
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CSU_CSLX_GDI,
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CSU_CSLX_DDI,
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CSU_CSLX_RESERVED1,
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CSU_CSLX_USB3_PHY = 117,
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CSU_CSLX_RESERVED2,
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CSU_CSLX_MAX,
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};
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struct csu_ns_dev {
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unsigned long ind;
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uint32_t val;
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};
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void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
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#endif
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