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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
534 lines
14 KiB
C
534 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk322x.h>
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#include <asm/arch/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3228-cru.h>
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#include <linux/log2.h>
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enum {
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VCO_MAX_HZ = 3200U * 1000000,
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VCO_MIN_HZ = 800 * 1000000,
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OUTPUT_MAX_HZ = 3200U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk322x_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static void rkclk_init(struct rk322x_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select gpll as pd_bus bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
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hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
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aclk_div << BUS_ACLK_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
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pclk_div << BUS_PCLK_DIV_SHIFT |
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hclk_div << BUS_HCLK_DIV_SHIFT);
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/*
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* select gpll as pd_peri bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
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PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_NORM << GPLL_MODE_SHIFT |
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APLL_MODE_NORM << APLL_MODE_SHIFT);
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con;
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int pll_id = rk_pll_id(clk_id);
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struct rk322x_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
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GPLL_MODE_SHIFT, 0xff
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};
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static u32 clk_mask[CLK_COUNT] = {
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0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
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GPLL_MODE_MASK, 0xff
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};
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uint shift;
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uint mask;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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mask = clk_mask[clk_id];
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switch ((con & mask) >> shift) {
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case GPLL_MODE_SLOW:
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return OSC_HZ;
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case GPLL_MODE_NORM:
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/* normal mode */
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con = readl(&pll->con0);
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postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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con = readl(&pll->con1);
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postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
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int periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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con = readl(&cru->cru_clksel_con[12]);
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
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div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
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return DIV_TO_RATE(src_rate, div) / 2;
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}
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static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
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{
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ulong ret;
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/*
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* The gmac clock can be derived either from an external clock
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* or can be generated from internally by a divider from SCLK_MAC.
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*/
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if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
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/* An external clock will always generate the right rate... */
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ret = freq;
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} else {
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u32 con = readl(&cru->cru_clksel_con[5]);
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ulong pll_rate;
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u8 div;
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if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
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pll_rate = GPLL_HZ;
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else
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/* CPLL is not set */
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return -EPERM;
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div = DIV_ROUND_UP(pll_rate, freq) - 1;
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if (div <= 0x1f)
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rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
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div << CLK_MAC_DIV_SHIFT);
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else
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debug("Unsupported div for gmac:%d\n", div);
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return DIV_TO_RATE(pll_rate, div);
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}
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return ret;
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}
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static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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int mux;
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debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
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/* mmc clock defaulg div 2 internal, need provide double in cru */
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src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
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if (src_clk_div > 128) {
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src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
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assert(src_clk_div - 1 < 128);
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mux = EMMC_SEL_24M;
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} else {
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mux = EMMC_SEL_GPLL;
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}
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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EMMC_PLL_MASK,
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mux << EMMC_PLL_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_DIV_MASK,
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
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mux << MMC0_PLL_SHIFT |
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
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}
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static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
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{
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struct pll_div dpll_cfg;
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/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
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switch (set_rate) {
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case 400*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
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break;
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case 600*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
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break;
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case 800*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
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break;
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}
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
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DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
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DPLL_MODE_NORM << DPLL_MODE_SHIFT);
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return set_rate;
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}
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static ulong rk322x_clk_get_rate(struct clk *clk)
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{
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struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
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ulong rate, gclk_rate;
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gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
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switch (clk->id) {
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case 0 ... 63:
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rate = rkclk_pll_get_rate(priv->cru, clk->id);
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break;
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case HCLK_EMMC:
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case SCLK_EMMC:
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
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break;
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default:
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return -ENOENT;
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}
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return rate;
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}
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static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
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ulong new_rate, gclk_rate;
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gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
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switch (clk->id) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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clk->id, rate);
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break;
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case CLK_DDR:
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new_rate = rk322x_ddr_set_clk(priv->cru, rate);
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break;
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case SCLK_MAC:
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new_rate = rk322x_mac_set_clk(priv->cru, rate);
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break;
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case PLL_GPLL:
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return 0;
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default:
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return -ENOENT;
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}
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return new_rate;
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}
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static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
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{
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struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
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struct rk322x_cru *cru = priv->cru;
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/*
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* If the requested parent is in the same clock-controller and the id
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* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
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*/
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if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
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debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
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rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
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return 0;
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}
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/*
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* If the requested parent is in the same clock-controller and the id
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* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
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*/
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if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
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debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
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rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
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return 0;
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}
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return -EINVAL;
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}
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static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
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{
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struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
|
|
const char *clock_output_name;
|
|
struct rk322x_cru *cru = priv->cru;
|
|
int ret;
|
|
|
|
ret = dev_read_string_index(parent->dev, "clock-output-names",
|
|
parent->id, &clock_output_name);
|
|
if (ret < 0)
|
|
return -ENODATA;
|
|
|
|
if (!strcmp(clock_output_name, "ext_gmac")) {
|
|
debug("%s: switching gmac extclk to ext_gmac\n", __func__);
|
|
rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
|
|
return 0;
|
|
} else if (!strcmp(clock_output_name, "phy_50m_out")) {
|
|
debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
|
|
rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
switch (clk->id) {
|
|
case SCLK_MAC:
|
|
return rk322x_gmac_set_parent(clk, parent);
|
|
case SCLK_MAC_EXTCLK:
|
|
return rk322x_gmac_extclk_set_parent(clk, parent);
|
|
}
|
|
|
|
debug("%s: unsupported clk %ld\n", __func__, clk->id);
|
|
return -ENOENT;
|
|
}
|
|
|
|
static struct clk_ops rk322x_clk_ops = {
|
|
.get_rate = rk322x_clk_get_rate,
|
|
.set_rate = rk322x_clk_set_rate,
|
|
.set_parent = rk322x_clk_set_parent,
|
|
};
|
|
|
|
static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rk322x_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk322x_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk322x_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
rkclk_init(priv->cru);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk322x_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct udevice *sys_child;
|
|
struct sysreset_reg *priv;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
&sys_child);
|
|
if (ret) {
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
} else {
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
|
|
cru_glb_srst_fst_value);
|
|
priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
|
|
cru_glb_srst_snd_value);
|
|
sys_child->priv = priv;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
|
|
ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
|
|
ret = rockchip_reset_bind(dev, ret, 9);
|
|
if (ret)
|
|
debug("Warning: software reset driver bind faile\n");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rk322x_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3228-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk322x_cru) = {
|
|
.name = "clk_rk322x",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk322x_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
|
|
.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
|
|
.ops = &rk322x_clk_ops,
|
|
.bind = rk322x_clk_bind,
|
|
.probe = rk322x_clk_probe,
|
|
};
|