mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6d0e34bf4e
The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
138 lines
2.9 KiB
C
138 lines
2.9 KiB
C
/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <asm/arch/clk.h>
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#define ATMEL_SDHC_MIN_FREQ 400000
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#ifndef CONFIG_DM_MMC
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int atmel_sdhci_init(void *regbase, u32 id)
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{
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struct sdhci_host *host;
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u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
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host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
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if (!host) {
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printf("%s: sdhci_host calloc failed\n", __func__);
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return -ENOMEM;
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}
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host->name = "atmel_sdhci";
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host->ioaddr = regbase;
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host->quirks = 0;
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max_clk = at91_get_periph_generated_clk(id);
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if (!max_clk) {
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printf("%s: Failed to get the proper clock\n", __func__);
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free(host);
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return -ENODEV;
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}
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host->max_clk = max_clk;
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add_sdhci(host, 0, min_clk);
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return 0;
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}
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#else
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DECLARE_GLOBAL_DATA_PTR;
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struct atmel_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int atmel_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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u32 max_clk;
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u32 caps, caps_1;
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u32 clk_base, clk_mul;
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ulong gck_rate;
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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host->name = dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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host->quirks = 0;
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"bus-width", 4);
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caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
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caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
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clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
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gck_rate = clk_base * 1000000 * (clk_mul + 1);
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return ret;
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ret = clk_set_rate(&clk, gck_rate);
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if (ret)
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return ret;
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max_clk = clk_get_rate(&clk);
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if (!max_clk)
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return -EINVAL;
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host->max_clk = max_clk;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
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if (ret)
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return ret;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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host->mmc->priv = host;
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upriv->mmc = host->mmc;
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clk_free(&clk);
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return sdhci_probe(dev);
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}
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static int atmel_sdhci_bind(struct udevice *dev)
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{
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struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id atmel_sdhci_ids[] = {
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{ .compatible = "atmel,sama5d2-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(atmel_sdhci_drv) = {
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.name = "atmel_sdhci",
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.id = UCLASS_MMC,
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.of_match = atmel_sdhci_ids,
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.ops = &sdhci_ops,
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.bind = atmel_sdhci_bind,
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.probe = atmel_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
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};
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#endif
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