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https://github.com/brain-hackers/u-boot-brain
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c40b6df87f
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
102 lines
3.7 KiB
C
102 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Copyright (C) 2018 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
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#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
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#include <linux/types.h>
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/* DIVQ_VALUES: number of valid DIVQ values */
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#define DIVQ_VALUES 6
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/*
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* Bit definitions for struct analogbits_wrpll_cfg.flags
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*
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* WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
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* programmed to enter bypass
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* WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
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* WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
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* feedback mode
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* WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
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* feedback mode (not yet supported by this driver)
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*
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* The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are
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* mutually exclusive. If both bits are set, or both are zero, the struct
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* analogbits_wrpll_cfg record is uninitialized or corrupt.
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*/
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#define WRPLL_FLAGS_BYPASS_SHIFT 0
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#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
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#define WRPLL_FLAGS_RESET_SHIFT 1
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#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
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#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
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#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
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#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
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#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
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/**
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* struct analogbits_wrpll_cfg - WRPLL configuration values
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* @divr: reference divider value (6 bits), as presented to the PLL signals.
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* @divf: feedback divider value (9 bits), as presented to the PLL signals.
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* @divq: output divider value (3 bits), as presented to the PLL signals.
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* @flags: PLL configuration flags. See above for more information.
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* @range: PLL loop filter range. See below for more information.
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* @_output_rate_cache: cached output rates, swept across DIVQ.
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* @_parent_rate: PLL refclk rate for which values are valid
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* @_max_r: maximum possible R divider value, given @parent_rate
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* @_init_r: initial R divider value to start the search from
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*
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* @divr, @divq, @divq, @range represent what the PLL expects to see
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* on its input signals. Thus @divr and @divf are the actual divisors
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* minus one. @divq is a power-of-two divider; for example, 1 =
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* divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
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*
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* When initially passing a struct analogbits_wrpll_cfg record, the
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* record should be zero-initialized with the exception of the @flags
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* field. The only flag bits that need to be set are either
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* WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
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*
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* Field names beginning with an underscore should be considered
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* private to the wrpll-cln28hpc.c code.
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*/
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struct analogbits_wrpll_cfg {
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u8 divr;
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u8 divq;
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u8 range;
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u8 flags;
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u16 divf;
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u32 _output_rate_cache[DIVQ_VALUES];
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unsigned long _parent_rate;
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u8 _max_r;
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u8 _init_r;
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};
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/*
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* Function prototypes
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*/
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int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
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u32 target_rate,
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unsigned long parent_rate);
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unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c);
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unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
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unsigned long parent_rate);
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#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
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