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c40b6df87f
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
20 lines
501 B
Plaintext
20 lines
501 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CLK_ANALOGBITS_WRPLL_CLN28HPC
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bool
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config CLK_SIFIVE
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bool "SiFive SoC driver support"
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depends on CLK
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help
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SoC drivers for SiFive Linux-capable SoCs.
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config CLK_SIFIVE_FU540_PRCI
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bool "PRCI driver for SiFive FU540 SoCs"
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depends on CLK_SIFIVE
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select CLK_ANALOGBITS_WRPLL_CLN28HPC
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help
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Supports the Power Reset Clock interface (PRCI) IP block found in
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FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
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enable this driver.
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