mirror of
https://github.com/brain-hackers/u-boot-brain
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1f47e2aca4
common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXoxw9wAKCRDKSWXLKUoM IbQxAKCK23yTy4FoN8oTGTYsbmLOA9kVUQCbBx8lg4nBeA8ihSaAnY+HMDF37YI= =Lg54 -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.07 common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver Signed-off-by: Tom Rini <trini@konsulko.com> |
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| .. | ||
| altera | ||
| analogbits | ||
| aspeed | ||
| at91 | ||
| exynos | ||
| imx | ||
| intel | ||
| mediatek | ||
| meson | ||
| mtmips | ||
| mvebu | ||
| owl | ||
| renesas | ||
| rockchip | ||
| sifive | ||
| sunxi | ||
| tegra | ||
| uniphier | ||
| clk_bcm6345.c | ||
| clk_boston.c | ||
| clk_fixed_factor.c | ||
| clk_fixed_rate.c | ||
| clk_pic32.c | ||
| clk_sandbox_ccf.c | ||
| clk_sandbox_test.c | ||
| clk_sandbox.c | ||
| clk_stm32f.c | ||
| clk_stm32h7.c | ||
| clk_stm32mp1.c | ||
| clk_versal.c | ||
| clk_vexpress_osc.c | ||
| clk_zynq.c | ||
| clk_zynqmp.c | ||
| clk-cdce9xx.c | ||
| clk-composite.c | ||
| clk-divider.c | ||
| clk-fixed-factor.c | ||
| clk-gate.c | ||
| clk-hsdk-cgu.c | ||
| clk-mux.c | ||
| clk-ti-sci.c | ||
| clk-uclass.c | ||
| clk.c | ||
| ics8n3qv01.c | ||
| Kconfig | ||
| Makefile | ||
| mpc83xx_clk.c | ||
| mpc83xx_clk.h | ||