mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
f5e2466f7b
R2D plus is SH reference board used with SH7751R. This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface, one PCI bus, VGA, and two Ethernet controller. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
155 lines
2.9 KiB
ArmAsm
155 lines
2.9 KiB
ArmAsm
/*
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* modified from SH-IPL+g (init-r0p751rlc0011rl.S)
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* Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
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* Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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mov.l CCR_A, r1
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mov.l CCR_D_D, r0
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mov.l r0,@r1
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mov.l MMUCR_A,r1
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mov.l MMUCR_D,r0
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mov.w r0,@r1
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mov.l BCR1_A,r1
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mov.l BCR1_D,r0
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mov.l r0,@r1
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mov.l BCR2_A,r1
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mov.l BCR2_D,r0
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mov.w r0,@r1
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mov.l BCR3_A,r1
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mov.l BCR3_D,r0
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mov.w r0,@r1
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mov.l BCR4_A,r1
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mov.l BCR4_D,r0
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mov.l r0,@r1
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mov.l WCR1_A,r1
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mov.l WCR1_D,r0
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mov.l r0,@r1
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mov.l WCR2_A,r1
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mov.l WCR2_D,r0
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mov.l r0,@r1
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mov.l WCR3_A,r1
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mov.l WCR3_D,r0
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mov.l r0,@r1
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mov.l PCR_A,r1
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mov.l PCR_D,r0
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mov.w r0,@r1
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mov.l LED_A,r1
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mov #0xff,r0
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mov.w r0,@r1
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mov.l MCR_A,r1
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mov.l MCR_D1,r0
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mov.l r0,@r1
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mov.l RTCNT_A,r1
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mov.l RTCNT_D,r0
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mov.w r0,@r1
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mov.l RTCOR_A,r1
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mov.l RTCOR_D,r0
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mov.w r0,@r1
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mov.l RFCR_A,r1
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mov.l RFCR_D,r0
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mov.w r0,@r1
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mov.l RTCSR_A,r1
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mov.l RTCSR_D,r0
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mov.w r0,@r1
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mov.l SDMR3_A,r1
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mov #0x55,r0
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mov.b r0,@r1
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/* Wait DRAM refresh 30 times */
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mov.l RFCR_A,r1
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mov #30,r3
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1:
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mov.w @r1,r0
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extu.w r0,r2
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cmp/hi r3,r2
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bf 1b
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mov.l MCR_A,r1
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mov.l MCR_D2,r0
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mov.l r0,@r1
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mov.l SDMR3_A,r1
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mov #0,r0
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mov.b r0,@r1
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mov.l IRLMASK_A,r1
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mov.l IRLMASK_D,r0
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mov.l r0,@r1
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mov.l CCR_A, r1
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mov.l CCR_D_E, r0
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mov.l r0, @r1
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rts
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nop
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.align 2
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CCR_A: .long CCR /* Cache Control Register */
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CCR_D_D: .long 0x0808 /* Flush the cache, disable */
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CCR_D_E: .long 0x8000090B
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FRQCR_A: .long FRQCR /* FRQCR Address */
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FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
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BCR1_A: .long BCR1 /* BCR1 Address */
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BCR1_D: .long 0x00180008
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BCR2_A: .long BCR2 /* BCR2 Address */
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BCR2_D: .long 0xabe8
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BCR3_A: .long BCR3 /* BCR3 Address */
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BCR3_D: .long 0x0000
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BCR4_A: .long BCR4 /* BCR4 Address */
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BCR4_D: .long 0x00000010
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WCR1_A: .long WCR1 /* WCR1 Address */
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WCR1_D: .long 0x33343333
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WCR2_A: .long WCR2 /* WCR2 Address */
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WCR2_D: .long 0xcff86fbf
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WCR3_A: .long WCR3 /* WCR3 Address */
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WCR3_D: .long 0x07777707
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LED_A: .long 0x04000036 /* LED Address */
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RTCNT_A: .long RTCNT /* RTCNT Address */
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RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
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RTCOR_A: .long RTCOR /* RTCOR Address */
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RTCOR_D: .long 0xA534 /* RTCOR Write Code */
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RTCSR_A: .long RTCSR /* RTCSR Address */
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RTCSR_D: .long 0xA510 /* RTCSR Write Code */
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SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
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SDMR3_D: .long 0x55
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MCR_A: .long MCR /* MCR Address */
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MCR_D1: .long 0x081901F4 /* MRSET:'0' */
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MCR_D2: .long 0x481901F4 /* MRSET:'1' */
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RFCR_A: .long RFCR /* RFCR Address */
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RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
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PCR_A: .long PCR /* PCR Address */
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PCR_D: .long 0x0000
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MMUCR_A: .long MMUCR /* MMUCCR Address */
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MMUCR_D: .long 0x00000000 /* MMUCCR Data */
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IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
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IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
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