Dave Gerlach b56b9a0884 ARM: AM43xx: Change DDR3 Reset Value ... The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>		2014-03-04 09:42:07 -05:00
..
board.c	ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control	2014-02-21 13:55:40 -05:00
clock_am33xx.c	ARM: AM43xx: clocks: Update DPLL details	2013-12-18 21:14:01 -05:00
clock_am43xx.c	ARM: AM43xx: clocks: Enable CPGMAC clock control	2014-03-04 09:42:06 -05:00
clock_ti814x.c	ti814x: Fix illegal use of FP ops in clock_ti814x.c	2014-02-21 14:03:44 -05:00
clock_ti816x.c	Add TI816X support	2013-08-15 18:38:37 -04:00
clock.c	ARM: AM43xx: clocks: Update DPLL details	2013-12-18 21:14:01 -05:00
config.mk	kbuild: use shorten logs for mkimage rules	2014-02-25 11:01:29 -05:00
ddr.c	ARM: AM43xx: Write sdram_config to secure_emif_sdram_config	2014-03-04 09:42:07 -05:00
emif4.c	ARM: AM43xx: Change DDR3 Reset Value	2014-03-04 09:42:07 -05:00
Makefile	mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms	2013-11-21 13:33:41 -06:00
mem.c	am335x: fix GPMC config for NAND and NOR SPL boot	2013-11-21 13:33:41 -06:00
mux.c	am33xx: move generic parts of pinmux handling out from board/ti/am335x	2012-10-25 11:31:37 -07:00
sys_info.c	am335x_evm: am33xx_spl_board_init function and scale core frequency	2013-09-20 16:57:35 -04:00
u-boot-spl.lds	arm: make _end compiler-generated	2014-02-26 21:18:09 +01:00