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![Eugeniy Paltsev](/assets/img/avatar_default.png)
Current DW SPI driver uses 32 bit access for some registers and 16 bit access for others. So if DW SPI IP is connected via bus which doesn't support 16 bit access we will get bus error. Fix that by switching to 32 bit access only instead of 16 and 32 bit mix Additional Documentation to Support this Change: The DW_apb_ssi databook states: "All registers in the DW_apb_ssi are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from these bits returns 0." [1] [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
507 lines
12 KiB
C
507 lines
12 KiB
C
/*
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* Designware master SPI core controller driver
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*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* Very loosely based on the Linux driver:
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* drivers/spi/spi-dw.c, which is:
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* Copyright (c) 2009, Intel Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <asm-generic/gpio.h>
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include <linux/compat.h>
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#include <linux/iopoll.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Register offsets */
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#define DW_SPI_CTRL0 0x00
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#define DW_SPI_CTRL1 0x04
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#define DW_SPI_SSIENR 0x08
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#define DW_SPI_MWCR 0x0c
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#define DW_SPI_SER 0x10
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#define DW_SPI_BAUDR 0x14
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#define DW_SPI_TXFLTR 0x18
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#define DW_SPI_RXFLTR 0x1c
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#define DW_SPI_TXFLR 0x20
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#define DW_SPI_RXFLR 0x24
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#define DW_SPI_SR 0x28
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#define DW_SPI_IMR 0x2c
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#define DW_SPI_ISR 0x30
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#define DW_SPI_RISR 0x34
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#define DW_SPI_TXOICR 0x38
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#define DW_SPI_RXOICR 0x3c
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#define DW_SPI_RXUICR 0x40
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#define DW_SPI_MSTICR 0x44
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#define DW_SPI_ICR 0x48
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#define DW_SPI_DMACR 0x4c
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#define DW_SPI_DMATDLR 0x50
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#define DW_SPI_DMARDLR 0x54
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#define DW_SPI_IDR 0x58
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#define DW_SPI_VERSION 0x5c
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#define DW_SPI_DR 0x60
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
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#define SR_BUSY BIT(0)
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#define SR_TF_NOT_FULL BIT(1)
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#define SR_TF_EMPT BIT(2)
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#define SR_RF_NOT_EMPT BIT(3)
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#define SR_RF_FULL BIT(4)
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#define SR_TX_ERR BIT(5)
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#define SR_DCOL BIT(6)
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#define RX_TIMEOUT 1000 /* timeout in ms */
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struct dw_spi_platdata {
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s32 frequency; /* Default clock frequency, -1 for none */
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void __iomem *regs;
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};
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struct dw_spi_priv {
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void __iomem *regs;
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unsigned int freq; /* Default frequency */
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unsigned int mode;
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struct clk clk;
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unsigned long bus_clk_rate;
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struct gpio_desc cs_gpio; /* External chip-select gpio */
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int bits_per_word;
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u8 cs; /* chip select pin */
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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int len;
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u32 fifo_len; /* depth of the FIFO buffer */
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void *tx;
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void *tx_end;
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void *rx;
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void *rx_end;
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};
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static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
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{
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return __raw_readl(priv->regs + offset);
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}
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static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
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{
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__raw_writel(val, priv->regs + offset);
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}
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static int request_gpio_cs(struct udevice *bus)
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{
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#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
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struct dw_spi_priv *priv = dev_get_priv(bus);
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int ret;
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/* External chip select gpio line is optional */
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ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
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if (ret == -ENOENT)
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return 0;
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if (ret < 0) {
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printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
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return ret;
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}
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if (dm_gpio_is_valid(&priv->cs_gpio)) {
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dm_gpio_set_dir_flags(&priv->cs_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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}
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debug("%s: used external gpio for CS management\n", __func__);
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#endif
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return 0;
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}
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static int dw_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct dw_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
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plat->frequency);
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return request_gpio_cs(bus);
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}
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static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
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{
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dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
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}
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/* Restart the controller, disable all interrupts, clean rx fifo */
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static void spi_hw_init(struct dw_spi_priv *priv)
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{
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spi_enable_chip(priv, 0);
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dw_write(priv, DW_SPI_IMR, 0xff);
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spi_enable_chip(priv, 1);
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/*
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* Try to detect the FIFO depth if not set by interface driver,
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* the depth could be from 2 to 256 from HW spec
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*/
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if (!priv->fifo_len) {
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u32 fifo;
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for (fifo = 1; fifo < 256; fifo++) {
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dw_write(priv, DW_SPI_TXFLTR, fifo);
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if (fifo != dw_read(priv, DW_SPI_TXFLTR))
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break;
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}
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priv->fifo_len = (fifo == 1) ? 0 : fifo;
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dw_write(priv, DW_SPI_TXFLTR, 0);
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}
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debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
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}
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/*
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* We define dw_spi_get_clk function as 'weak' as some targets
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* (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
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* and implement dw_spi_get_clk their own way in their clock manager.
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*/
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__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
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{
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struct dw_spi_priv *priv = dev_get_priv(bus);
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int ret;
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
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return ret;
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*rate = clk_get_rate(&priv->clk);
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if (!*rate)
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goto err_rate;
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debug("%s: get spi controller clk via device tree: %lu Hz\n",
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__func__, *rate);
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return 0;
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err_rate:
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clk_disable(&priv->clk);
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clk_free(&priv->clk);
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return -EINVAL;
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}
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static int dw_spi_probe(struct udevice *bus)
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{
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struct dw_spi_platdata *plat = dev_get_platdata(bus);
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struct dw_spi_priv *priv = dev_get_priv(bus);
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int ret;
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priv->regs = plat->regs;
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priv->freq = plat->frequency;
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ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
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if (ret)
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return ret;
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/* Currently only bits_per_word == 8 supported */
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priv->bits_per_word = 8;
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priv->tmode = 0; /* Tx & Rx */
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/* Basic HW init */
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spi_hw_init(priv);
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return 0;
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}
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/* Return the max entries we can fill into tx fifo */
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static inline u32 tx_max(struct dw_spi_priv *priv)
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{
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u32 tx_left, tx_room, rxtx_gap;
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tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
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tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
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/*
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* Another concern is about the tx/rx mismatch, we
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* thought about using (priv->fifo_len - rxflr - txflr) as
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* one maximum value for tx, but it doesn't cover the
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* data which is out of tx/rx fifo and inside the
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* shift registers. So a control from sw point of
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* view is taken.
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*/
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rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
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(priv->bits_per_word >> 3);
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return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
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}
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/* Return the max entries we should read out of rx fifo */
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static inline u32 rx_max(struct dw_spi_priv *priv)
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{
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u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
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return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
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}
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static void dw_writer(struct dw_spi_priv *priv)
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{
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u32 max = tx_max(priv);
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u16 txw = 0;
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while (max--) {
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/* Set the tx word if the transfer's original "tx" is not null */
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if (priv->tx_end - priv->len) {
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if (priv->bits_per_word == 8)
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txw = *(u8 *)(priv->tx);
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else
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txw = *(u16 *)(priv->tx);
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}
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dw_write(priv, DW_SPI_DR, txw);
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debug("%s: tx=0x%02x\n", __func__, txw);
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priv->tx += priv->bits_per_word >> 3;
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}
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}
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static void dw_reader(struct dw_spi_priv *priv)
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{
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u32 max = rx_max(priv);
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u16 rxw;
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while (max--) {
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rxw = dw_read(priv, DW_SPI_DR);
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debug("%s: rx=0x%02x\n", __func__, rxw);
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/* Care about rx if the transfer's original "rx" is not null */
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if (priv->rx_end - priv->len) {
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if (priv->bits_per_word == 8)
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*(u8 *)(priv->rx) = rxw;
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else
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*(u16 *)(priv->rx) = rxw;
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}
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priv->rx += priv->bits_per_word >> 3;
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}
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}
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static int poll_transfer(struct dw_spi_priv *priv)
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{
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do {
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dw_writer(priv);
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dw_reader(priv);
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} while (priv->rx_end > priv->rx);
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return 0;
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}
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static void external_cs_manage(struct udevice *dev, bool on)
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{
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#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
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struct dw_spi_priv *priv = dev_get_priv(dev->parent);
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if (!dm_gpio_is_valid(&priv->cs_gpio))
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return;
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dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
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#endif
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}
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static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct dw_spi_priv *priv = dev_get_priv(bus);
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const u8 *tx = dout;
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u8 *rx = din;
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int ret = 0;
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u32 cr0 = 0;
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u32 val;
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u32 cs;
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/* spi core configured to do 8 bit transfers */
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if (bitlen % 8) {
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debug("Non byte aligned SPI transfer.\n");
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return -1;
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}
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/* Start the transaction if necessary. */
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if (flags & SPI_XFER_BEGIN)
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external_cs_manage(dev, false);
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cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
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(priv->mode << SPI_MODE_OFFSET) |
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(priv->tmode << SPI_TMOD_OFFSET);
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if (rx && tx)
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priv->tmode = SPI_TMOD_TR;
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else if (rx)
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priv->tmode = SPI_TMOD_RO;
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else
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/*
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* In transmit only mode (SPI_TMOD_TO) input FIFO never gets
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* any data which breaks our logic in poll_transfer() above.
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*/
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priv->tmode = SPI_TMOD_TR;
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cr0 &= ~SPI_TMOD_MASK;
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cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
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priv->len = bitlen >> 3;
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debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
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priv->tx = (void *)tx;
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priv->tx_end = priv->tx + priv->len;
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priv->rx = rx;
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priv->rx_end = priv->rx + priv->len;
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/* Disable controller before writing control registers */
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spi_enable_chip(priv, 0);
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debug("%s: cr0=%08x\n", __func__, cr0);
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/* Reprogram cr0 only if changed */
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if (dw_read(priv, DW_SPI_CTRL0) != cr0)
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dw_write(priv, DW_SPI_CTRL0, cr0);
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/*
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* Configure the desired SS (slave select 0...3) in the controller
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* The DW SPI controller will activate and deactivate this CS
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* automatically. So no cs_activate() etc is needed in this driver.
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*/
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cs = spi_chip_select(dev);
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dw_write(priv, DW_SPI_SER, 1 << cs);
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/* Enable controller after writing control registers */
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spi_enable_chip(priv, 1);
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/* Start transfer in a polling loop */
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ret = poll_transfer(priv);
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/*
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* Wait for current transmit operation to complete.
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* Otherwise if some data still exists in Tx FIFO it can be
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* silently flushed, i.e. dropped on disabling of the controller,
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* which happens when writing 0 to DW_SPI_SSIENR which happens
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* in the beginning of new transfer.
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*/
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if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
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!(val & SR_TF_EMPT) || (val & SR_BUSY),
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RX_TIMEOUT * 1000)) {
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ret = -ETIMEDOUT;
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}
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/* Stop the transaction if necessary */
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if (flags & SPI_XFER_END)
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external_cs_manage(dev, true);
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return ret;
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}
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static int dw_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct dw_spi_platdata *plat = bus->platdata;
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struct dw_spi_priv *priv = dev_get_priv(bus);
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u16 clk_div;
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if (speed > plat->frequency)
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speed = plat->frequency;
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/* Disable controller before writing control registers */
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spi_enable_chip(priv, 0);
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/* clk_div doesn't support odd number */
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clk_div = priv->bus_clk_rate / speed;
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clk_div = (clk_div + 1) & 0xfffe;
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dw_write(priv, DW_SPI_BAUDR, clk_div);
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/* Enable controller after writing control registers */
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spi_enable_chip(priv, 1);
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priv->freq = speed;
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debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
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priv->freq, clk_div);
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return 0;
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}
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static int dw_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct dw_spi_priv *priv = dev_get_priv(bus);
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/*
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* Can't set mode yet. Since this depends on if rx, tx, or
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* rx & tx is requested. So we have to defer this to the
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* real transfer function.
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*/
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops dw_spi_ops = {
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.xfer = dw_spi_xfer,
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.set_speed = dw_spi_set_speed,
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.set_mode = dw_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id dw_spi_ids[] = {
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{ .compatible = "snps,dw-apb-ssi" },
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{ }
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};
|
|
|
|
U_BOOT_DRIVER(dw_spi) = {
|
|
.name = "dw_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = dw_spi_ids,
|
|
.ops = &dw_spi_ops,
|
|
.ofdata_to_platdata = dw_spi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct dw_spi_priv),
|
|
.probe = dw_spi_probe,
|
|
};
|