mirror of
https://github.com/brain-hackers/u-boot-brain
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0cd9465c0b
With the generic omap3-u-boot.dtsi file available, this patch increased the memory of the various incarnations of the omap3_logic board, and points their respective u-boot.dtsi files to the newly created generic one, and removes the PLATDATA from the board file. These are all done at once because the're all utilizing the same omap3logic.c board file. Signed-off-by: Adam Ford <aford173@gmail.com>
239 lines
6.3 KiB
C
239 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* Logic Product Development <www.logicpd.com>
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*
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* Author :
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* Peter Barada <peter.barada@logicpd.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <netdev.h>
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#include <flash.h>
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#include <nand.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/omap_mmc.h>
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#include <asm/mach-types.h>
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#include <linux/mtd/rawnand.h>
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#include <asm/omap_musb.h>
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#include <linux/errno.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/musb.h>
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#include "omap3logic.h"
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#ifdef CONFIG_USB_EHCI_HCD
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
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#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
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#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* 200 MHz works for OMAP36/DM37 */
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/* 256MB DDR */
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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} else {
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/* 165 MHz works for OMAP35 */
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timings->mcfg = MICRON_V_MCFG_165(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
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#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
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#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
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void spl_board_prepare_for_linux(void)
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{
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/* The Micron NAND starts locked which
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* prohibits mounting the NAND as RW
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* The following commands are what unlocks
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* the NAND to become RW Falcon Mode does not
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* have as many smarts as U-Boot, but Logic PD
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* only makes NAND with 512MB so these hard coded
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* values should work for all current models
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*/
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writeb(0x70, GPMC_NAND_COMMAND_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(0x7a, GPMC_NAND_COMMAND_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_COMMAND_0);
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/* Begin address 0 */
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writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_DATA_0);
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/* Ending address at the end of Flash */
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writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
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writeb(0xc0, GPMC_NAND_ADDRESS_0);
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writeb(0xff, GPMC_NAND_ADDRESS_0);
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writeb(0x03, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(0x79, GPMC_NAND_COMMAND_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(-1, GPMC_NAND_DATA_0);
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}
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#endif
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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omap_die_id_display();
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return 0;
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}
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#if defined(CONFIG_FLASH_CFI_DRIVER)
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static const u32 gpmc_dm37_c2nor_config[] = {
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
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LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
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};
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static const u32 gpmc_omap35_c2nor_config[] = {
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
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LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
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};
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#endif
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_FLASH_CFI_DRIVER)
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Enable CS2 for NOR Flash */
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enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
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0x10000000, GPMC_SIZE_64M);
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} else {
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enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
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0x10000000, GPMC_SIZE_64M);
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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static void unlock_nand(void)
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{
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int dev = nand_curr_device;
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struct mtd_info *mtd;
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mtd = get_nand_dev_by_index(dev);
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nand_unlock(mtd, 0, mtd->size, 0);
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
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unlock_nand();
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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#ifdef CONFIG_SMC911X
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/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
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static const u32 gpmc_lan92xx_config[] = {
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NET_LAN92XX_GPMC_CONFIG1,
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NET_LAN92XX_GPMC_CONFIG2,
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NET_LAN92XX_GPMC_CONFIG3,
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NET_LAN92XX_GPMC_CONFIG4,
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NET_LAN92XX_GPMC_CONFIG5,
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NET_LAN92XX_GPMC_CONFIG6,
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};
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int board_eth_init(bd_t *bis)
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{
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enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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}
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#endif
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