mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
4a87fea6de
This patch allows to switch the CPU frequency to 800MHz on the ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM using the STM32MP15x SOC and when it is supported by the HW (for STM32MP15xD and STM32MP15xF). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
191 lines
2.3 KiB
Plaintext
191 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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pinctrl0 = &pinctrl;
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pinctrl1 = &pinctrl_z;
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};
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clocks {
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u-boot,dm-pre-reloc;
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};
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/* need PSCI for sysreset during board_f */
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psci {
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u-boot,dm-pre-proper;
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};
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reboot {
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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ddr: ddr@5a003000 {
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-ddr";
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reg = <0x5A003000 0x550
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0x5A004000 0x234>;
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRC2>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrc2",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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status = "okay";
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};
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};
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};
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&bsec {
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u-boot,dm-pre-reloc;
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};
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&clk_csi {
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u-boot,dm-pre-reloc;
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};
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&clk_hsi {
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u-boot,dm-pre-reloc;
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};
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&clk_hse {
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u-boot,dm-pre-reloc;
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};
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&clk_lsi {
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u-boot,dm-pre-reloc;
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};
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&clk_lse {
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u-boot,dm-pre-reloc;
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};
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&cpu0_opp_table {
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u-boot,dm-spl;
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opp-650000000 {
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u-boot,dm-spl;
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};
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opp-800000000 {
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u-boot,dm-spl;
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};
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};
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&gpioa {
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u-boot,dm-pre-reloc;
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};
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&gpiob {
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u-boot,dm-pre-reloc;
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};
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&gpioc {
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u-boot,dm-pre-reloc;
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};
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&gpiod {
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u-boot,dm-pre-reloc;
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};
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&gpioe {
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u-boot,dm-pre-reloc;
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};
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&gpiof {
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u-boot,dm-pre-reloc;
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};
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&gpiog {
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u-boot,dm-pre-reloc;
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};
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&gpioh {
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u-boot,dm-pre-reloc;
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};
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&gpioi {
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u-boot,dm-pre-reloc;
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};
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&gpioj {
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u-boot,dm-pre-reloc;
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};
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&gpiok {
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u-boot,dm-pre-reloc;
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};
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&gpioz {
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u-boot,dm-pre-reloc;
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};
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&iwdg2 {
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u-boot,dm-pre-reloc;
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};
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/* pre-reloc probe = reserve video frame buffer in video_reserve() */
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<dc {
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u-boot,dm-pre-proper;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_z {
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u-boot,dm-pre-reloc;
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};
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&pwr_regulators {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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&sdmmc1 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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};
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&sdmmc2 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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};
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&sdmmc3 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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};
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&usbotg_hs {
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compatible = "st,stm32mp1-hsotg", "snps,dwc2";
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};
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