mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 07:43:45 +09:00
5b0055547f
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
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| .. | ||
| config.mk | ||
| cpu_init.c | ||
| cpu.c | ||
| ecc.c | ||
| fdt.c | ||
| interrupts.c | ||
| Makefile | ||
| nand_init.c | ||
| pci.c | ||
| pcie.c | ||
| qe_io.c | ||
| serdes.c | ||
| spd_sdram.c | ||
| speed.c | ||
| start.S | ||
| traps.c | ||
| u-boot.lds | ||