mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 22:56:17 +09:00
1e6b07c649
Make ecc initialisation robust, as DDR2-ECC errors may be generated while zeroing the RAM. Return 16 bytes (a cacheline) less than the available memory, as the board and/or PPC440EPx might have problems accessing the last bytes. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> |
||
|---|---|---|
| .. | ||
| common | ||
| hcu4 | ||
| hcu5 | ||