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https://github.com/brain-hackers/u-boot-brain
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6228e6389e
The patch adds EMIF-A macros for setting chip select parameters Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EMIF_DEFS_H_
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#define _EMIF_DEFS_H_
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#include <asm/arch/hardware.h>
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typedef struct davinci_emif_regs {
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dv_reg ERCSR;
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dv_reg AWCCR;
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dv_reg SDBCR;
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dv_reg SDRCR;
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dv_reg AB1CR;
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dv_reg AB2CR;
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dv_reg AB3CR;
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dv_reg AB4CR;
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dv_reg SDTIMR;
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dv_reg DDRSR;
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dv_reg DDRPHYCR;
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dv_reg DDRPHYSR;
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dv_reg TOTAR;
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dv_reg TOTACTR;
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dv_reg DDRPHYID_REV;
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dv_reg SDSRETR;
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dv_reg EIRR;
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dv_reg EIMR;
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dv_reg EIMSR;
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dv_reg EIMCR;
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dv_reg IOCTRLR;
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dv_reg IOSTATR;
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u_int8_t RSVD0[8];
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dv_reg NANDFCR;
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dv_reg NANDFSR;
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u_int8_t RSVD1[8];
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dv_reg NANDFECC[4];
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u_int8_t RSVD2[60];
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dv_reg NAND4BITECCLOAD;
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dv_reg NAND4BITECC1;
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dv_reg NAND4BITECC2;
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dv_reg NAND4BITECC3;
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dv_reg NAND4BITECC4;
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dv_reg NANDERRADD1;
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dv_reg NANDERRADD2;
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dv_reg NANDERRVAL1;
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dv_reg NANDERRVAL2;
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} emif_registers;
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typedef emif_registers *emifregs;
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#define davinci_emif_regs \
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((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
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#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
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#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
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#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
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#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
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/* Chip Select setup */
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#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
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#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
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#define DAVINCI_ABCR_WSETUP(n) (n << 26)
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#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
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#define DAVINCI_ABCR_WHOLD(n) (n << 17)
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#define DAVINCI_ABCR_RSETUP(n) (n << 13)
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#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
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#define DAVINCI_ABCR_RHOLD(n) (n << 4)
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#define DAVINCI_ABCR_TA(n) (n << 2)
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#define DAVINCI_ABCR_ASIZE_16BIT 1
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#define DAVINCI_ABCR_ASIZE_8BIT 0
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#endif
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