mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
67482f57e6
ARC HS Development Kit board is a new low-cost
development platform sporting ARC HS38 in real silicon
with nice set of features such as:
* Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz
* 4Gb of DDR (we use only lowest 1Gb out of it now)
* Lots of DesigWare peripherals
* Different connectivity modules:
- Synopsys HAPS HT3
- Arduino-compatible connector
- MikroBUS
This initial commit supports the following peripherals:
* UART (DW 8250)
* Ethernet (DW GMAC)
* SD/MMC (DW Mobile Storage)
* USB 1.1 & 2.0
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
146 lines
2.8 KiB
Plaintext
146 lines
2.8 KiB
Plaintext
menu "ARC architecture"
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depends on ARC
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config SYS_ARCH
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default "arc"
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config SYS_CPU
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default "arcv1" if ISA_ARCOMPACT
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default "arcv2" if ISA_ARCV2
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choice
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prompt "ARC Instruction Set"
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default ISA_ARCOMPACT
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config ISA_ARCOMPACT
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bool "ARCompact ISA"
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help
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The original ARC ISA of ARC600/700 cores
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config ISA_ARCV2
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bool "ARC ISA v2"
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help
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ISA for the Next Generation ARC-HS cores
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endchoice
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choice
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prompt "CPU selection"
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default CPU_ARC770D if ISA_ARCOMPACT
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default CPU_ARCHS38 if ISA_ARCV2
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config CPU_ARC750D
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bool "ARC 750D"
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select ARC_MMU_V2
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depends on ISA_ARCOMPACT
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help
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Choose this option to build an U-Boot for ARC750D CPU.
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config CPU_ARC770D
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bool "ARC 770D"
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select ARC_MMU_V3
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depends on ISA_ARCOMPACT
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help
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Choose this option to build an U-Boot for ARC770D CPU.
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config CPU_ARCEM6
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bool "ARC EM6"
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select ARC_MMU_ABSENT
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depends on ISA_ARCV2
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS36
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bool "ARC HS36"
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select ARC_MMU_ABSENT
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depends on ISA_ARCV2
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS38
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bool "ARC HS38"
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select ARC_MMU_V4
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depends on ISA_ARCV2
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help
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Next Generation ARC Core based on ISA-v2 ISA with MMU.
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endchoice
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choice
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prompt "MMU Version"
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default ARC_MMU_V3 if CPU_ARC770D
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default ARC_MMU_V2 if CPU_ARC750D
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default ARC_MMU_ABSENT if CPU_ARCEM6
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default ARC_MMU_ABSENT if CPU_ARCHS36
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default ARC_MMU_V4 if CPU_ARCHS38
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config ARC_MMU_ABSENT
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bool "No MMU"
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help
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No MMU
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config ARC_MMU_V2
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bool "MMU v2"
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depends on CPU_ARC750D
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help
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Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
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when 2 D-TLB and 1 I-TLB entries index into same 2way set.
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config ARC_MMU_V3
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bool "MMU v3"
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depends on CPU_ARC770D
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help
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Introduced with ARC700 4.10: New Features
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
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Shared Address Spaces (SASID)
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config ARC_MMU_V4
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bool "MMU v4"
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depends on CPU_ARCHS38
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help
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Introduced as a part of ARC HS38 release.
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endchoice
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config CPU_BIG_ENDIAN
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bool "Enable Big Endian Mode"
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default n
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help
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Build kernel for Big Endian Mode of ARC CPU
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config SYS_ICACHE_OFF
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bool "Do not use Instruction Cache"
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default n
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config SYS_DCACHE_OFF
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bool "Do not use Data Cache"
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default n
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choice
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prompt "Target select"
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default TARGET_AXS103
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config TARGET_TB100
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bool "Support tb100"
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config TARGET_NSIM
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bool "Support standalone nSIM & Free nSIM"
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config TARGET_AXS101
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bool "Support Synopsys Designware SDP board AXS101"
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config TARGET_AXS103
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bool "Support Synopsys Designware SDP board AXS103"
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config TARGET_HSDK
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bool "Support Synpsys HS DevelopmentKit board"
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endchoice
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source "board/abilis/tb100/Kconfig"
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source "board/synopsys/Kconfig"
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source "board/synopsys/axs10x/Kconfig"
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source "board/synopsys/hsdk/Kconfig"
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endmenu
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