mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
167 lines
3.7 KiB
C
167 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* WORK Microwave work_92105 board configuration file
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*/
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#ifndef __CONFIG_WORK_92105_H__
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#define __CONFIG_WORK_92105_H__
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/* SoC and board defines */
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#include <linux/sizes.h>
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#include <asm/arch/cpu.h>
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/*
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* Define work_92105 machine type by hand -- done only for compatibility
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* with original board code
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*/
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#define CONFIG_MACH_TYPE 736
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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/* generate LPC32XX-specific SPL image */
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#define CONFIG_LPC32XX_SPL
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_MALLOC_LEN SZ_1M
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#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
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#define CONFIG_SYS_SDRAM_SIZE SZ_128M
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
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- GENERATED_GBL_DATA_SIZE)
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/*
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* Serial Driver
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*/
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#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
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/*
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* Ethernet Driver
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*/
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#define CONFIG_PHY_SMSC
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#define CONFIG_LPC32XX_ETH
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
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/*
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* I2C driver
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*/
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#define CONFIG_SYS_I2C_LPC32XX
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SPEED 350000
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/*
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* I2C EEPROM
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/*
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* I2C RTC
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*/
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#define CONFIG_RTC_DS1374
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/*
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* U-Boot General Configurations
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*/
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* NAND chip timings for FIXME: which one?
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*/
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#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
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#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
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#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
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#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
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#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
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#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
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#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
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/*
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* NAND
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*/
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/* driver configuration */
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_CHIPS 1
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#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
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#define CONFIG_NAND_LPC32XX_MLC
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/*
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* GPIO
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*/
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#define CONFIG_LPC32XX_GPIO
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/*
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* SSP/SPI/DISPLAY
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*/
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#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
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/*
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* Environment
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*/
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#define CONFIG_ENV_SIZE 0x00020000
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#define CONFIG_ENV_OFFSET 0x00100000
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#define CONFIG_ENV_OFFSET_REDUND 0x00120000
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#define CONFIG_ENV_ADDR 0x80000100
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/*
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* Boot Linux
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*/
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR 0x80008000
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/*
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* SPL
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*/
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/* SPL will be executed at offset 0 */
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#define CONFIG_SPL_TEXT_BASE 0x00000000
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/* SPL will use SRAM as stack */
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#define CONFIG_SPL_STACK 0x0000FFF8
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/* Use the framework and generic lib */
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/* SPL will use serial */
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/* SPL will load U-Boot from NAND offset 0x40000 */
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
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#define CONFIG_SPL_PAD_TO 0x20000
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/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
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#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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/*
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* Include SoC specific configuration
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*/
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#include <asm/arch/config.h>
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#endif /* __CONFIG_WORK_92105_H__*/
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