mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
456 lines
13 KiB
C
456 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006.
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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/*
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* ve8313 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_MPC831x 1
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#define CONFIG_MPC8313 1
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#define CONFIG_PCI_INDIRECT_BRIDGE 1
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#define CONFIG_FSL_ELBC 1
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/*
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* On-board devices
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*
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*/
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#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#define CONFIG_SYS_IMMR 0xE0000000
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#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x07000000
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
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/*
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* Device configurations
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*/
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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/*
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* Manually set up DDR parameters, as this board does not
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* have the SPD connected to I2C.
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_AP \
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| CSCONFIG_ODT_RD_NEVER \
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| CSCONFIG_ODT_WR_ALL \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80840102 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (3 << TIMING_CFG0_RRT_SHIFT) \
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| (2 << TIMING_CFG0_WWT_SHIFT) \
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| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x0e720802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (6 << TIMING_CFG1_REFREC_SHIFT) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x26256222 */
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#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (5 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x029028c7 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03202000 */
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_32)
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/* 0x43080000 */
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0232 << SDRAM_MODE_SD_SHIFT))
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/* 0x44400232 */
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#define CONFIG_SYS_DDR_MODE_2 0x8000C000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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/*0x02000000*/
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_NOMZ \
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| DDRCDR_NZ_NOMZ \
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| DDRCDR_M_ODR)
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/* 0x73000002 */
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
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#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
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| BR_PS_16 /* 16 bit */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV4 \
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| OR_GPCM_SCY_5 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EAD)
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/* 0xfe000c55 */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* NAND settings
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*/
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#define CONFIG_SYS_NAND_BASE 0x61000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
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#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
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| BR_PS_8 \
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| BR_DECC_CHK_GEN \
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| BR_MS_FCM \
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| BR_V) /* valid */
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/* 0x61000c21 */
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
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| OR_FCM_BCTLD \
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| OR_FCM_CHT \
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| OR_FCM_SCY_2 \
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| OR_FCM_RST \
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| OR_FCM_TRLX)
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/* 0xffff90ac */
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
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#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
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/* CS2 NvRAM */
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#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
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| BR_PS_8 \
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| BR_V)
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/* 0x60000801 */
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#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
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| OR_GPCM_CSNT \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_3 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xfffe0937 */
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/* local bus read write buffer mapping SRAM@0x64000000 */
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#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
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| BR_PS_16 \
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| BR_V)
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/* 0x62001001 */
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#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
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| OR_GPCM_CSNT \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xfe0009f7 */
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif
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/*
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* TSEC
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*/
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#define CONFIG_TSEC1
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC1"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x01
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#define TSEC1_FLAGS 0
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#define TSEC1_PHYIDX 0
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#endif
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Environment
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*/
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x4000
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/* 0x64050000 */
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#define CONFIG_SYS_HRCW_LOW (\
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0x20000000 /* reserved, must be set */ |\
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HRCWL_DDRCM |\
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HRCWL_CSB_TO_CLKIN_4X1 | \
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HRCWL_CORE_TO_CSB_2_5X1)
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/* 0xa0600004 */
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#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
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HRCWH_PCI_ARBITER_ENABLE | \
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_TSEC1M_IN_MII | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_EARLY)
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/* System IO Config */
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#define CONFIG_SYS_SICRH (0x01000000 | \
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SICRH_ETSEC2_B | \
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SICRH_ETSEC2_C | \
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SICRH_ETSEC2_D | \
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SICRH_ETSEC2_E | \
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SICRH_ETSEC2_F | \
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SICRH_ETSEC2_G | \
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SICRH_TSOBI1 | \
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SICRH_TSOBI2)
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/* 0x010fff03 */
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#define CONFIG_SYS_SICRL (SICRL_LBC | \
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SICRL_SPI_A | \
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SICRL_SPI_B | \
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SICRL_SPI_C | \
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SICRL_SPI_D | \
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SICRL_ETSEC2_A)
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/* 0x33fc0003) */
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR @ 0x00000000 */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#if defined(CONFIG_PCI)
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/* PCI @ 0x80000000 */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATL_PP_RW \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#else
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#define CONFIG_SYS_IBAT1L (0)
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#define CONFIG_SYS_IBAT1U (0)
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#define CONFIG_SYS_IBAT2L (0)
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#define CONFIG_SYS_IBAT2U (0)
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#endif
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/* PCI2 not supported on 8313 */
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#define CONFIG_SYS_IBAT3L (0)
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#define CONFIG_SYS_IBAT3U (0)
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#define CONFIG_SYS_IBAT4L (0)
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#define CONFIG_SYS_IBAT4U (0)
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
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| BATL_PP_RW \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
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#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* FPGA, SRAM, NAND @ 0x60000000 */
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#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#define CONFIG_NETDEV eth0
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#define CONFIG_HOSTNAME "ve8313"
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#define CONFIG_UBOOTPATH ve8313/u-boot.bin
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" __stringify(CONFIG_NETDEV) "\0" \
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"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
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"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"u-boot_addr_r=100000\0" \
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"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
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" +${filesize};" \
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"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
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"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
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" ${filesize};" \
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"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
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#endif /* __CONFIG_H */
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