mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the sh7757lcr board
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*/
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#ifndef __SH7757LCR_H
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#define __SH7757LCR_H
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#define CONFIG_CPU_SH7757 1
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#define CONFIG_SH7757LCR_DDR_ECC 1
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#define SH7757LCR_SDRAM_BASE (0x80000000)
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#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
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#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
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#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_CONS_SCIF2 1
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#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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224 * 1024 * 1024)
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 + 16) * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 1
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
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#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
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#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
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#define SH7757LCR_ETHERNET_MAC_SIZE 17
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#define SH7757LCR_ETHERNET_NUM_CH 2
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/* Gigabit Ether */
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#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
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/* SPI */
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#define CONFIG_SH_SPI_BASE 0xfe002000
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/* MMCIF */
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#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
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#define CONFIG_SH_MMCIF_CLK 48000000
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/* SH7757 board */
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#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
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#define SH7757LCR_GRA_OFFSET 0x1f000000
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#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
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#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
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#define SH7757LCR_PCIEBRG_ADDR 0x00090000
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#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
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/* ENV setting */
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#define CONFIG_ENV_IS_EMBEDDED
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_ADDR (0x00080000)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netboot=bootp; bootm\0"
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 48000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __SH7757LCR_H */
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