mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
259 lines
6.1 KiB
C
259 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
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#define CONFIG_SYS_FSL_CLK
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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/*
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* DDR: 800 MHz ( 1600 MT/s data rate )
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*/
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI \
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board/freescale/ls1021aiot/ls102xa_pbi.cfg
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#endif
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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/*
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* I2C
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*/
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/*
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* MMC
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*/
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#define CONFIG_CMD_MMC
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/* SATA */
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#define CONFIG_SCSI_AHCI_PLAT
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#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
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#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
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#endif
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#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
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PCI_DEVICE_ID_FREESCALE_AHCI}
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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/* SPI */
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SPI_FLASH_SPANSION
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/* QSPI */
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#define QSPI0_AMBA_BASE 0x40000000
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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#define CONFIG_SPI_FLASH_BAR
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#define CONFIG_SPI_FLASH_SPANSION
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#endif
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/* DM SPI */
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#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
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#define CONFIG_CMD_SF
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#define CONFIG_DM_SPI_FLASH
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#endif
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/*
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* eTSEC
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*/
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII
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#define CONFIG_MII_DEFAULT_TSEC 1
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC1_PHY_ADDR 1
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC2"
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#endif
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/* PCIe */
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#define CONFIG_PCIE1 /* PCIE controler 1 */
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#define CONFIG_PCIE2 /* PCIE controler 2 */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#define CONFIG_CMD_MII
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_high=0xffffffff\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMD_GREPENV
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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#define CONFIG_LS102XA_STREAM_ID
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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/* start of monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#endif
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#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SD_BOOT)
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#endif
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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#define CONFIG_MISC_INIT_R
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#include <asm/fsl_secure_boot.h>
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#endif
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