mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Sysam AMCORE board configuration
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*
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* (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
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*/
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#ifndef __AMCORE_CONFIG_H
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#define __AMCORE_CONFIG_H
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#define CONFIG_HOSTNAME "AMCORE"
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT 0
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BOOTCOMMAND "bootm ffc20000"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"upgrade_uboot=loady; " \
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"protect off 0xffc00000 0xffc1ffff; " \
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"erase 0xffc00000 0xffc1ffff; " \
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"cp.b 0x20000 0xffc00000 ${filesize}\0" \
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"upgrade_kernel=loady; " \
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"erase 0xffc20000 0xffefffff; " \
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"cp.b 0x20000 0xffc20000 ${filesize}\0" \
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"upgrade_jffs2=loady; " \
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"erase 0xfff00000 0xffffffff; " \
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"cp.b 0x20000 0xfff00000 ${filesize}\0"
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/* undef to save memory */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x0
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#define CONFIG_SYS_MEMTEST_END 0x1000000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CLK 45000000
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#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
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/* Register Base Addrs */
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#define CONFIG_SYS_MBAR 0x10000000
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/* Definitions for initial stack pointer and data area (in DPRAM) */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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/* size of internal SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 0x1000000
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#define CONFIG_SYS_FLASH_BASE 0xffc00000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/* amcore design has flash data bytes wired swapped */
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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/* reserve 128-4KB */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text*);
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/* memory map space for linux boot data */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* Cache Configuration
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*
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* Special 8K version 3 core cache.
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* This is a single unified instruction/data cache.
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* sdram - single region - no masks
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
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#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
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CF_ACR_EN)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
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CF_CACR_EC)
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/* CS0 - AMD Flash, address 0xffc00000 */
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#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
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/* 4MB, AA=0,V=1 C/I BIT for errata */
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#define CONFIG_SYS_CS0_MASK 0x003f0001
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/* WS=10, AA=1, PS=16bit (10) */
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#define CONFIG_SYS_CS0_CTRL 0x1980
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/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
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#define CONFIG_SYS_CS1_BASE 0x3000
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#define CONFIG_SYS_CS1_MASK 0x00070001
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#define CONFIG_SYS_CS1_CTRL 0x0100
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#endif /* __AMCORE_CONFIG_H */
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