mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
357 lines
12 KiB
C
357 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Authors: Roy Zang <tie-fei.zang@freescale.com>
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* Chunhe Lan <Chunhe.Lan@freescale.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/* High Level Configuration Options */
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_HWCONFIG
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x02000000
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/* Implement conversion of addresses in the LBC */
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
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/* DDR Setup */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_DDR_SPD
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#define CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x50
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#define CONFIG_SYS_DDR_RAW_TIMING
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/*
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* Memory map
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*
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* 0x0000_0000 0x1fff_ffff DDR 512M cacheable
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* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
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* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
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*
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* Localbus non-cacheable
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*
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* 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
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* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/* NAND flash config */
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
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| OR_FCM_PGS \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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/* Serial Port */
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#endif
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 3, Slot 1, tgtid 3, Base address b000 */
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#define CONFIG_SYS_PCIE3_NAME "Slot 3"
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "Slot 2"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "Slot 1"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#ifdef CONFIG_HAS_FSL_DR_USB
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#endif
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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/* Qman/Bman */
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#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
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#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
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CONFIG_SYS_QMAN_CENA_SIZE)
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
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#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
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CONFIG_SYS_BMAN_CENA_SIZE)
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
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/* For FM */
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHY_ATHEROS
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#endif
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/* Default address of microcode for the Linux Fman driver */
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/* QE microcode/firmware address */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#ifdef CONFIG_FMAN_ENET
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#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
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#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
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#define CONFIG_SYS_TBIPA_VALUE 8
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_ETHPRIME "FM1@DTSEC1"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"loadaddr=1000000\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off $ubootaddr +$filesize; " \
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"erase $ubootaddr +$filesize; " \
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"cp.b $loadaddr $ubootaddr $filesize; " \
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"protect on $ubootaddr +$filesize; " \
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"cmp.b $loadaddr $ubootaddr $filesize\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"fdtfile=p1023rdb.dtb\0" \
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"othbootargs=ramdisk_size=600000\0" \
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"bdev=sda1\0" \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#endif /* __CONFIG_H */
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