mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
249 lines
7.9 KiB
C
249 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Freescale MCF5485 FireEngine board.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5485EVB_H
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#define _M5485EVB_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#undef CONFIG_HW_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
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#define CONFIG_SLTTMR
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#define CONFIG_FSLDMAFEC
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#ifdef CONFIG_FSLDMAFEC
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# define CONFIG_MII 1
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# define CONFIG_MII_INIT 1
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# define CONFIG_HAS_ETH1
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# define CONFIG_SYS_DMA_USE_INTSRAM 1
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# define CONFIG_SYS_DISCOVER_PHY
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# define CONFIG_SYS_RX_ETH_BUFFER 32
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# define CONFIG_SYS_TX_ETH_BUFFER 48
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_SYS_FEC0_PINMUX 0
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# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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# define CONFIG_SYS_FEC1_PINMUX 0
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# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CONFIG_SYS_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CONFIG_SYS_DISCOVER_PHY */
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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#endif
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#ifdef CONFIG_CMD_USB
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# define CONFIG_USB_OHCI_NEW
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/*# define CONFIG_PCI_OHCI*/
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# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
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# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
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# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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/* PCI */
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCI_IO_BUS 0x71000000
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#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
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#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
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#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
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#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
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#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
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#endif
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#define CONFIG_UDP_CHECKSUM
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#define CONFIG_HOSTNAME "M548xEVB"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off bank 1;" \
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"era ff800000 ff83ffff;" \
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"cp.b ${loadaddr} ff800000 ${filesize};"\
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"save\0" \
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""
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
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#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
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#define CONFIG_SYS_INTSRAMSZ 0x8000
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/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM_CTRL 0x21
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#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
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#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_CFG1 0x73711630
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#define CONFIG_SYS_SDRAM_CFG2 0x46770000
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#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
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#define CONFIG_SYS_SDRAM_EMOD 0x40010000
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#define CONFIG_SYS_SDRAM_MODE 0x018D0000
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#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
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#ifdef CONFIG_SYS_DRAMSZ1
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# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
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#else
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# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
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#endif
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
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#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
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/* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_CFI
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#ifdef CONFIG_SYS_FLASH_CFI
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# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
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# define CONFIG_FLASH_CFI_DRIVER 1
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# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
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# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#ifdef CONFIG_SYS_NOR1SZ
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# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
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# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
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#else
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# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
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#endif
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#endif
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/* Configuration for environment
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* Environment is not embedded in u-boot. First time runing may have env
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* crc error warning if there is no correct environment on the flash.
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*/
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
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CF_CACR_IDCM)
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#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
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#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
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CF_CACR_IEC | CF_CACR_ICINVA)
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#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
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CF_CACR_DEC | CF_CACR_DDCM_P | \
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CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
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/*-----------------------------------------------------------------------
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* Chipselect bank definitions
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*/
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/*
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* CS0 - NOR Flash 1, 2, 4, or 8MB
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* CS1 - NOR Flash
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* CS2 - Available
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* CS3 - Available
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* CS4 - Available
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* CS5 - Available
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*/
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#define CONFIG_SYS_CS0_BASE 0xFF800000
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#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
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#define CONFIG_SYS_CS0_CTRL 0x00101980
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#ifdef CONFIG_SYS_NOR1SZ
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#define CONFIG_SYS_CS1_BASE 0xE0000000
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#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
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#define CONFIG_SYS_CS1_CTRL 0x00101D80
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#endif
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#endif /* _M5485EVB_H */
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