mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Freescale MCF5208EVBe.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef _M5208EVBE_H
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#define _M5208EVBE_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#undef CONFIG_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 5000
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_MII 1
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# define CONFIG_MII_INIT 1
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# define CONFIG_SYS_DISCOVER_PHY
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# define CONFIG_SYS_RX_ETH_BUFFER 8
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_HAS_ETH1
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# define CONFIG_SYS_FEC0_PINMUX 0
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# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CONFIG_SYS_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CONFIG_SYS_DISCOVER_PHY */
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#endif
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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#ifdef CONFIG_MCFFEC
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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#endif /* CONFIG_MCFFEC */
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#define CONFIG_HOSTNAME "M5208EVBe"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=40010000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off 0 3ffff;" \
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"era 0 3ffff;" \
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"cp.b ${loadaddr} 0 ${filesize};" \
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"save\0" \
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""
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CONFIG_SYS_LOAD_ADDR 0x40010000
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#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
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#define CONFIG_SYS_PLL_ODR 0x36
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#define CONFIG_SYS_PLL_FDR 0x7D
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#define CONFIG_SYS_MBAR 0xFC000000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/* Definitions for initial stack pointer and data area (in DPRAM) */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM_CTRL 0x221
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
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#define CONFIG_SYS_SDRAM_CFG1 0x43711630
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#define CONFIG_SYS_SDRAM_CFG2 0x56670000
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#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
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#define CONFIG_SYS_SDRAM_EMOD 0x80010000
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#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
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#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_CFI
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#ifdef CONFIG_SYS_FLASH_CFI
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# define CONFIG_FLASH_CFI_DRIVER 1
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# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
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# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
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# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#endif
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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/*
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* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#define CONFIG_ENV_OFFSET 0x2000
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text*);
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
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CF_CACR_DISD | CF_CACR_INVI | \
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CF_CACR_CEIB | CF_CACR_DCM | \
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CF_CACR_EUSP)
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/* Chipselect bank definitions */
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/*
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* CS0 - NOR Flash
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* CS1 - Available
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* CS2 - Available
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* CS3 - Available
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* CS4 - Available
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* CS5 - Available
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*/
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#define CONFIG_SYS_CS0_BASE 0
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#define CONFIG_SYS_CS0_MASK 0x007F0001
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#define CONFIG_SYS_CS0_CTRL 0x00001FA0
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#endif /* _M5208EVBE_H */
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