mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 20:39:43 +09:00
1dff14c87d
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
||
|---|---|---|
| .. | ||
| arm11 | ||
| arm720t | ||
| arm920t | ||
| arm926ejs | ||
| arm946es | ||
| arm1136 | ||
| arm1176 | ||
| armv7 | ||
| armv7m | ||
| armv8 | ||
| pxa | ||
| sa1100 | ||
| Makefile | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||