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https://github.com/brain-hackers/u-boot-brain
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1dfdd9ba4e
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* for now: just dummy functions to satisfy the linker */
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#include <common.h>
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#include <malloc.h>
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__weak void flush_cache(unsigned long start, unsigned long size)
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{
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#if defined(CONFIG_CPU_ARM1136)
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#if !defined(CONFIG_SYS_ICACHE_OFF)
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asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
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#endif
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
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#endif
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#endif /* CONFIG_CPU_ARM1136 */
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#ifdef CONFIG_CPU_ARM926EJS
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/* test and clean, page 2-23 of arm926ejs manual */
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asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
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/* disable write buffer as well (page 2-22) */
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asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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#endif /* CONFIG_CPU_ARM926EJS */
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return;
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}
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/*
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* Default implementation:
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* do a range flush for the entire range
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*/
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__weak void flush_dcache_all(void)
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{
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flush_cache(0, ~0);
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}
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/*
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* Default implementation of enable_caches()
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* Real implementation should be in platform code
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*/
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__weak void enable_caches(void)
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{
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puts("WARNING: Caches not enabled\n");
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}
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#ifdef CONFIG_SYS_NONCACHED_MEMORY
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/*
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* Reserve one MMU section worth of address space below the malloc() area that
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* will be mapped uncached.
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*/
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static unsigned long noncached_start;
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static unsigned long noncached_end;
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static unsigned long noncached_next;
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void noncached_init(void)
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{
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phys_addr_t start, end;
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size_t size;
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end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
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size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
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start = end - size;
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debug("mapping memory %pa-%pa non-cached\n", &start, &end);
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noncached_start = start;
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noncached_end = end;
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noncached_next = start;
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#ifndef CONFIG_SYS_DCACHE_OFF
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mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
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#endif
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}
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phys_addr_t noncached_alloc(size_t size, size_t align)
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{
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phys_addr_t next = ALIGN(noncached_next, align);
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if (next >= noncached_end || (noncached_end - next) < size)
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return 0;
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debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
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noncached_next = next + size;
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return next;
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}
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#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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