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https://github.com/brain-hackers/u-boot-brain
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1df99080cb
MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>
47 lines
775 B
Makefile
47 lines
775 B
Makefile
#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright 2004 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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extra-y = start.o
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ifdef MINIMAL
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obj-y += spl_minimal.o
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else
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obj-y += traps.o
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obj-y += cpu.o
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obj-y += cpu_init.o
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obj-y += speed.o
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obj-y += interrupts.o
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obj-y += ecc.o
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obj-$(CONFIG_QE) += qe_io.o
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obj-$(CONFIG_FSL_SERDES) += serdes.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_PCIE) += pcie.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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# Stub implementations of cache management functions for USB
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obj-y += cache.o
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ifndef CONFIG_SYS_FSL_DDRC_GEN2
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obj-y += spd_sdram.o
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endif
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obj-$(CONFIG_SYS_FSL_DDR2) += law.o
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endif # not minimal
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