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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
206 lines
4.8 KiB
C
206 lines
4.8 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2006
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* Eric Schumann, Phytec Messtechnik GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <asm/io.h>
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#include "mt46v32m16-75.h"
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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{
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volatile struct mpc5xxx_cdm *cdm =
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(struct mpc5xxx_cdm *)MPC5XXX_CDM;
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volatile struct mpc5xxx_sdram *sdram =
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(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32 (&sdram->ctrl,
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(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
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/* precharge all banks */
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out_be32 (&sdram->ctrl,
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(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
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#ifdef SDRAM_DDR
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/* set mode register: extended mode */
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out_be32 (&sdram->mode, (SDRAM_EMODE));
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/* set mode register: reset DLL */
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out_be32 (&sdram->mode,
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(SDRAM_MODE | 0x04000000));
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#endif
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/* precharge all banks */
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out_be32 (&sdram->ctrl,
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(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
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/* auto refresh */
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out_be32 (&sdram->ctrl,
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(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
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/* set mode register */
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out_be32 (&sdram->mode, (SDRAM_MODE));
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/* normal operation */
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out_be32 (&sdram->ctrl,
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(SDRAM_CONTROL | hi_addr_bit));
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/* set CDM clock enable register, set MPC5200B SDRAM bus */
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/* to reduced driver strength */
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out_be32 (&cdm->clock_enable, (0x00CFFFFF));
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make
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* real use of CONFIG_SYS_SDRAM_BASE. The code does not
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* work if CONFIG_SYS_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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volatile struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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volatile struct mpc5xxx_cdm *cdm =
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(struct mpc5xxx_cdm *)MPC5XXX_CDM;
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volatile struct mpc5xxx_sdram *sdram =
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(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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/* 256MB at 0x0 */
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out_be32 (&mm->sdram0, 0x0000001b);
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/* disabled */
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out_be32 (&mm->sdram1, 0x10000000);
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/* setup config registers */
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out_be32 (&sdram->config1, SDRAM_CONFIG1);
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out_be32 (&sdram->config2, SDRAM_CONFIG2);
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#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
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/* set tap delay */
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out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
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sdram_start(1);
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test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else
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dramsize = test2;
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32 (&mm->sdram0,
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(0x13 + __builtin_ffs(dramsize >> 20) - 1));
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} else {
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/* disabled */
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out_be32 (&mm->sdram0, 0);
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32(&mm->sdram0) & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32(&mm->sdram1) & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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return dramsize + dramsize2;
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}
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int checkboard(void)
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{
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puts("Board: phyCORE-MPC5200B-tiny\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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return 0;
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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#define GPIO_PSC2_4 0x02000000UL
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void init_ide_reset(void)
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{
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volatile struct mpc5xxx_wu_gpio *wu_gpio =
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(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
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debug("init_ide_reset\n");
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/* Configure PSC2_4 as GPIO output for ATA reset */
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setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
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setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
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/* Deassert reset */
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setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
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}
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void ide_set_reset(int idereset)
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{
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volatile struct mpc5xxx_wu_gpio *wu_gpio =
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(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
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debug("ide_reset(%d)\n", idereset);
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if (idereset) {
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clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
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/* Make a delay. MPC5200 spec says 25 usec min */
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udelay(500000);
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} else
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setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
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}
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#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
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