mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
573 lines
13 KiB
C
573 lines
13 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <pci.h>
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#include <asm/fsl_serdes.h>
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#include <fsl_ifc.h>
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#include <asm/fsl_pci.h>
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#include <hwconfig.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO4_PCIE_RESET_SET 0x08000000
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#define MUX_CPLD_CAN_UART 0x00
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#define MUX_CPLD_TDM 0x01
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#define MUX_CPLD_SPICS0_FLASH 0x00
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#define MUX_CPLD_SPICS0_SLIC 0x02
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#define PMUXCR1_IFC_MASK 0x00ffff00
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#define PMUXCR1_SDHC_MASK 0x00fff000
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#define PMUXCR1_SDHC_ENABLE 0x00555000
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enum {
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MUX_TYPE_IFC,
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MUX_TYPE_SDHC,
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MUX_TYPE_SPIFLASH,
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MUX_TYPE_TDM,
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MUX_TYPE_CAN,
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MUX_TYPE_CS0_NOR,
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MUX_TYPE_CS0_NAND,
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};
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enum {
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I2C_READ_BANK,
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I2C_READ_PCB_VER,
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};
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static uint sd_ifc_mux;
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struct cpld_data {
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u8 cpld_ver; /* cpld revision */
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#if defined(CONFIG_P1010RDB_PA)
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u8 pcba_ver; /* pcb revision number */
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u8 twindie_ddr3;
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u8 res1[6];
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u8 bank_sel; /* NOR Flash bank */
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u8 res2[5];
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u8 usb2_sel;
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u8 res3[1];
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u8 porsw_sel;
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u8 tdm_can_sel;
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u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
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u8 por0; /* POR Options */
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u8 por1; /* POR Options */
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u8 por2; /* POR Options */
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u8 por3; /* POR Options */
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#elif defined(CONFIG_P1010RDB_PB)
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u8 rom_loc;
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#endif
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};
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int board_early_init_f(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
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/* Clock configuration to access CPLD using IFC(GPCM) */
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setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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/*
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* Reset PCIe slots via GPIO4
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*/
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setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
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setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_16M, 1);
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set_tlb(1, flashbase + 0x1000000,
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CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif /* ifdef CONFIG_PCI */
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int config_board_mux(int ctrl_type)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 tmp;
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#if defined(CONFIG_P1010RDB_PA)
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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switch (ctrl_type) {
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case MUX_TYPE_IFC:
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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tmp = 0xf0;
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i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
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tmp = 0x01;
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i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_IFC;
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clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
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break;
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case MUX_TYPE_SDHC:
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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tmp = 0xf0;
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i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
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tmp = 0x05;
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i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_SDHC;
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clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
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PMUXCR1_SDHC_ENABLE);
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break;
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case MUX_TYPE_SPIFLASH:
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out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
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break;
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case MUX_TYPE_TDM:
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
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out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
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break;
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case MUX_TYPE_CAN:
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out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
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break;
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default:
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break;
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}
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#elif defined(CONFIG_P1010RDB_PB)
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uint orig_bus = i2c_get_bus_num();
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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switch (ctrl_type) {
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case MUX_TYPE_IFC:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_IFC;
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clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
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break;
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case MUX_TYPE_SDHC:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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setbits_8(&tmp, 0x04);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x04);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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sd_ifc_mux = MUX_TYPE_SDHC;
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clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
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PMUXCR1_SDHC_ENABLE);
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break;
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case MUX_TYPE_SPIFLASH:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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clrbits_8(&tmp, 0x80);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x80);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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break;
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case MUX_TYPE_TDM:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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setbits_8(&tmp, 0x82);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x82);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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break;
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case MUX_TYPE_CAN:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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clrbits_8(&tmp, 0x02);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x02);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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break;
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case MUX_TYPE_CS0_NOR:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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break;
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case MUX_TYPE_CS0_NAND:
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
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setbits_8(&tmp, 0x08);
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i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
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i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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clrbits_8(&tmp, 0x08);
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
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break;
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default:
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break;
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}
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i2c_set_bus_num(orig_bus);
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#endif
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return 0;
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}
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#ifdef CONFIG_P1010RDB_PB
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int i2c_pca9557_read(int type)
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{
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u8 val;
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
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switch (type) {
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case I2C_READ_BANK:
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val = (val & 0x10) >> 4;
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break;
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case I2C_READ_PCB_VER:
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val = ((val & 0x60) >> 5) + 1;
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break;
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default:
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break;
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}
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return val;
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}
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#endif
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int checkboard(void)
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{
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struct cpu_type *cpu;
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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u8 val;
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cpu = gd->arch.cpu;
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#if defined(CONFIG_P1010RDB_PA)
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printf("Board: %sRDB-PA, ", cpu->name);
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#elif defined(CONFIG_P1010RDB_PB)
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printf("Board: %sRDB-PB, ", cpu->name);
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i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
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i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
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val = 0x0; /* no polarity inversion */
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i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
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#endif
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#ifdef CONFIG_SDCARD
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/* switch to IFC to read info from CPLD */
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config_board_mux(MUX_TYPE_IFC);
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#endif
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#if defined(CONFIG_P1010RDB_PA)
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val = (in_8(&cpld_data->pcba_ver) & 0xf);
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printf("PCB: v%x.0\n", val);
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#elif defined(CONFIG_P1010RDB_PB)
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val = in_8(&cpld_data->cpld_ver);
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printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
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printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
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val = in_8(&cpld_data->rom_loc) & 0xf;
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puts("Boot from: ");
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switch (val) {
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case 0xf:
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config_board_mux(MUX_TYPE_CS0_NOR);
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printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
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break;
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case 0xe:
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puts("SDHC\n");
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val = 0x60; /* set pca9557 pin input/output */
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i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
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break;
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case 0x5:
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config_board_mux(MUX_TYPE_IFC);
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config_board_mux(MUX_TYPE_CS0_NAND);
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puts("NAND\n");
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break;
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case 0x6:
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config_board_mux(MUX_TYPE_IFC);
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puts("SPI\n");
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break;
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default:
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puts("unknown\n");
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break;
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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struct cpu_type *cpu;
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int num = 0;
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cpu = gd->arch.cpu;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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/* P1014 and it's derivatives do not support eTSEC3 */
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if (cpu->soc_ver != SVR_P1014) {
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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num++;
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}
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void fdt_del_flexcan(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,p1010-flexcan")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_spi_flash(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"spansion,s25sl12801")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_spi_slic(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"zarlink,le88266")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_tdm(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,starlite-tdm")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_sdhc(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,esdhc")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_del_ifc(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,ifc")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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void fdt_disable_uart1(void *blob)
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{
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int nodeoff;
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nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
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CONFIG_SYS_NS16550_COM2);
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if (nodeoff > 0) {
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fdt_status_disabled(blob, nodeoff);
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} else {
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printf("WARNING unable to set status for fsl,ns16550 "
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"uart1: %s\n", fdt_strerror(nodeoff));
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}
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
phys_addr_t base;
|
|
phys_size_t size;
|
|
struct cpu_type *cpu;
|
|
|
|
cpu = gd->arch.cpu;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
base = getenv_bootm_low();
|
|
size = getenv_bootm_size();
|
|
|
|
#if defined(CONFIG_PCI)
|
|
FT_FSL_PCI_SETUP;
|
|
#endif
|
|
|
|
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
|
|
|
#if defined(CONFIG_HAS_FSL_DR_USB)
|
|
fdt_fixup_dr_usb(blob, bd);
|
|
#endif
|
|
|
|
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
|
|
if (cpu->soc_ver == SVR_P1014) {
|
|
fdt_del_flexcan(blob);
|
|
fdt_del_node_and_alias(blob, "ethernet2");
|
|
}
|
|
|
|
/* Delete IFC node as IFC pins are multiplexing with SDHC */
|
|
if (sd_ifc_mux != MUX_TYPE_IFC)
|
|
fdt_del_ifc(blob);
|
|
else
|
|
fdt_del_sdhc(blob);
|
|
|
|
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
|
|
fdt_del_tdm(blob);
|
|
fdt_del_spi_slic(blob);
|
|
} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
|
|
fdt_del_flexcan(blob);
|
|
fdt_del_spi_flash(blob);
|
|
fdt_disable_uart1(blob);
|
|
} else {
|
|
/*
|
|
* If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
|
|
* explicitly, defaultly spi_cs_sel to spi-flash instead of
|
|
* to tdm/slic.
|
|
*/
|
|
fdt_del_tdm(blob);
|
|
fdt_del_flexcan(blob);
|
|
fdt_disable_uart1(blob);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SDCARD
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
config_board_mux(MUX_TYPE_SDHC);
|
|
return -1;
|
|
}
|
|
#else
|
|
void board_reset(void)
|
|
{
|
|
/* mux to IFC to enable CPLD for reset */
|
|
if (sd_ifc_mux != MUX_TYPE_IFC)
|
|
config_board_mux(MUX_TYPE_IFC);
|
|
}
|
|
#endif
|
|
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
|
|
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
|
|
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
|
|
MPC85xx_PMUXCR_CAN1_UART |
|
|
MPC85xx_PMUXCR_CAN2_TDM |
|
|
MPC85xx_PMUXCR_CAN2_UART);
|
|
config_board_mux(MUX_TYPE_CAN);
|
|
} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
|
|
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
|
|
MPC85xx_PMUXCR_CAN1_UART);
|
|
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
|
|
MPC85xx_PMUXCR_CAN1_TDM);
|
|
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
|
|
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
|
|
config_board_mux(MUX_TYPE_TDM);
|
|
} else {
|
|
/* defaultly spi_cs_sel to flash */
|
|
config_board_mux(MUX_TYPE_SPIFLASH);
|
|
}
|
|
|
|
if (hwconfig("esdhc"))
|
|
config_board_mux(MUX_TYPE_SDHC);
|
|
else if (hwconfig("ifc"))
|
|
config_board_mux(MUX_TYPE_IFC);
|
|
|
|
#ifdef CONFIG_P1010RDB_PB
|
|
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
|
|
char * const argv[])
|
|
{
|
|
if (argc < 2)
|
|
return CMD_RET_USAGE;
|
|
if (strcmp(argv[1], "ifc") == 0)
|
|
config_board_mux(MUX_TYPE_IFC);
|
|
else if (strcmp(argv[1], "sdhc") == 0)
|
|
config_board_mux(MUX_TYPE_SDHC);
|
|
else
|
|
return CMD_RET_USAGE;
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
mux, 2, 0, pin_mux_cmd,
|
|
"configure multiplexing pin for IFC/SDHC bus in runtime",
|
|
"bus_type (e.g. mux sdhc)"
|
|
);
|