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626879b794
Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
66 lines
1.3 KiB
Plaintext
66 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include "skeleton.dtsi"
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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mck: mck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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sdmmc1: sdio-host@e1208000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1208000 0x300>;
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clocks = <&mck>, <&mck>, <&mck>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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uart0: serial@e1824200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xe1824200 0x200>;
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clocks = <&mck>;
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clock-names = "usart";
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status = "disabled";
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};
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};
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};
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};
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