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u-boot-brain/arch/powerpc/cpu
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Prabhakar Kushwaha e982746844 powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2 
CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
..
74xx_7xx Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
mpc5xx Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
mpc5xxx Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
mpc8xx Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
mpc8xxx powerpc: Use print_size() where appropriate 2013-08-20 10:37:58 -07:00
mpc83xx Coding Style cleanup: replace leading SPACEs by TABs 2013-10-14 16:06:54 -04:00
mpc85xx powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2 2013-10-16 16:13:11 -07:00
mpc86xx Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
mpc512x Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
mpc824x Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
mpc8260 Coding Style cleanup: remove trailing white space 2013-10-14 16:06:53 -04:00
ppc4xx Coding Style cleanup: replace leading SPACEs by TABs 2013-10-14 16:06:54 -04:00