mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 23:48:52 +09:00
315 lines
6.8 KiB
C
315 lines
6.8 KiB
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <sata.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <malloc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() == 3) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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/* Program freq register in System counter and enable system counter */
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writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
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ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr->counter_control_register);
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return 0;
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}
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
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defined(CONFIG_ZYNQ_EEPROM_BUS)
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i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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/*
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* fdt_get_reg - Fill buffer by information from DT
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*/
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static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
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const u32 *cell, int n)
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{
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int i = 0, b, banks;
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int parent_offset = fdt_parent_offset(fdt, nodeoffset);
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int address_cells = fdt_address_cells(fdt, parent_offset);
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int size_cells = fdt_size_cells(fdt, parent_offset);
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char *p = buf;
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u64 val;
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u64 vals;
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debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
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__func__, address_cells, size_cells, buf, cell);
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/* Check memory bank setup */
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banks = n % (address_cells + size_cells);
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if (banks)
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panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
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n, address_cells, size_cells);
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banks = n / (address_cells + size_cells);
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for (b = 0; b < banks; b++) {
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debug("%s: Bank #%d:\n", __func__, b);
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if (address_cells == 2) {
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val = cell[i + 1];
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val <<= 32;
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val |= cell[i];
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val = fdt64_to_cpu(val);
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debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
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__func__, val, p, &cell[i]);
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*(phys_addr_t *)p = val;
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} else {
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debug("%s: addr32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_addr_t);
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i += address_cells;
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debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
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sizeof(phys_addr_t));
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if (size_cells == 2) {
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vals = cell[i + 1];
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vals <<= 32;
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vals |= cell[i];
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vals = fdt64_to_cpu(vals);
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debug("%s: size64=%llx, ptr=%p, cell=%p\n",
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__func__, vals, p, &cell[i]);
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*(phys_size_t *)p = vals;
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} else {
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debug("%s: size32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_size_t);
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i += size_cells;
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debug("%s: ps=%p, i=%x, size=%zu\n",
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__func__, p, i, sizeof(phys_size_t));
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}
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/* Return the first address size */
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return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
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}
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#define FDT_REG_SIZE sizeof(u32)
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/* Temp location for sharing data for storing */
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/* Up to 64-bit address + 64-bit size */
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static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
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void dram_init_banksize(void)
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{
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int bank;
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memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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debug("Bank #%d: start %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].start);
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debug("Bank #%d: size %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].size);
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}
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}
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int dram_init(void)
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{
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int node, len;
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const void *blob = gd->fdt_blob;
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const u32 *cell;
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memset(&tmp, 0, sizeof(tmp));
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/* find or create "/memory" node. */
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node = fdt_subnode_offset(blob, 0, "memory");
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if (node < 0) {
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printf("%s: Can't get memory node\n", __func__);
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return node;
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}
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/* Get pointer to cells and lenght of it */
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell) {
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printf("%s: Can't get reg property\n", __func__);
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return -1;
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}
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gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
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debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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#endif
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void reset_cpu(ulong addr)
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{
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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void scsi_init(void)
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{
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#if defined(CONFIG_SATA_CEVA)
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init_sata(0);
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#endif
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ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
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scsi_scan(1);
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}
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#endif
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int board_late_init(void)
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{
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u32 reg = 0;
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u8 bootmode;
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const char *mode;
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char *new_targets;
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if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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debug("Saved variables - Skipping\n");
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return 0;
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}
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reg = readl(&crlapb_base->boot_mode);
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bootmode = reg & BOOT_MODES_MASK;
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puts("Bootmode: ");
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switch (bootmode) {
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case JTAG_MODE:
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puts("JTAG_MODE\n");
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mode = "pxe dhcp";
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break;
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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mode = "qspi0";
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puts("QSPI_MODE\n");
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break;
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case EMMC_MODE:
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puts("EMMC_MODE\n");
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mode = "mmc0";
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break;
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case SD_MODE:
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puts("SD_MODE\n");
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mode = "mmc0";
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break;
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case SD_MODE1:
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puts("SD_MODE1\n");
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#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
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mode = "mmc1";
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#else
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mode = "mmc0";
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#endif
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break;
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case NAND_MODE:
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puts("NAND_MODE\n");
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mode = "nand0";
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break;
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default:
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mode = "";
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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/*
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* One terminating char + one byte for space between mode
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* and default boot_targets
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*/
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new_targets = calloc(1, strlen(mode) +
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strlen(getenv("boot_targets")) + 2);
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sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
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setenv("boot_targets", new_targets);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Xilinx ZynqMP\n");
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return 0;
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}
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = ZYNQMP_USB0_XHCI_BASEADDR,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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};
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int usb_gadget_handle_interrupts(void)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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return dwc3_uboot_init(&dwc3_device_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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dwc3_uboot_exit(index);
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return 0;
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}
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#endif
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void reset_misc(void)
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{
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psci_system_reset(true);
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}
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