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https://github.com/brain-hackers/u-boot-brain
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![Bin Meng](/assets/img/avatar_default.png)
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
867 lines
23 KiB
C
867 lines
23 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fsl_dtsec.h>
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#include <asm/fsl_serdes.h>
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#include <hwconfig.h>
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#include "../common/qixis.h"
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#include "../common/fman.h"
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#include "t4240qds_qixis.h"
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#define EMI_NONE 0xFFFFFFFF
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#define EMI1_RGMII 0
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#define EMI1_SLOT1 1
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#define EMI1_SLOT2 2
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#define EMI1_SLOT3 3
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#define EMI1_SLOT4 4
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#define EMI1_SLOT5 5
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#define EMI1_SLOT7 7
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#define EMI2 8
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/* Slot6 and Slot8 do not have EMI connections */
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static int mdio_mux[NUM_FM_PORTS];
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static const char *mdio_names[] = {
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"T4240QDS_MDIO0",
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"T4240QDS_MDIO1",
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"T4240QDS_MDIO2",
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"T4240QDS_MDIO3",
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"T4240QDS_MDIO4",
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"T4240QDS_MDIO5",
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"NULL",
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"T4240QDS_MDIO7",
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"T4240QDS_10GC",
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};
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static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
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static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
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static u8 slot_qsgmii_phyaddr[5][4] = {
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{0, 0, 0, 0},/* not used, to make index match slot No. */
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{0, 1, 2, 3},
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{4, 5, 6, 7},
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{8, 9, 0xa, 0xb},
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{0xc, 0xd, 0xe, 0xf},
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};
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static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
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static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = t4240qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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struct t4240qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static void t4240qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if ((muxval < 6) || (muxval == 7)) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct t4240qds_mdio *priv = bus->priv;
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t4240qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct t4240qds_mdio *priv = bus->priv;
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t4240qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int t4240qds_mdio_reset(struct mii_dev *bus)
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{
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struct t4240qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int t4240qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct t4240qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate T4240QDS MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate T4240QDS private data\n");
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free(bus);
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return -1;
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}
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bus->read = t4240qds_mdio_read;
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bus->write = t4240qds_mdio_write;
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bus->reset = t4240qds_mdio_reset;
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strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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{
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int interface = fm_info_get_enet_if(port);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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if (interface == PHY_INTERFACE_MODE_SGMII ||
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interface == PHY_INTERFACE_MODE_QSGMII) {
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switch (port) {
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case FM1_DTSEC1:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy21");
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break;
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case FM1_DTSEC2:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy22");
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break;
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case FM1_DTSEC3:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy23");
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break;
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case FM1_DTSEC4:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy24");
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break;
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case FM1_DTSEC6:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy12");
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break;
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case FM1_DTSEC9:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy14");
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else
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fdt_set_phy_handle(blob, prop, pa,
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"phy_sgmii4");
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break;
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case FM1_DTSEC10:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy13");
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else
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fdt_set_phy_handle(blob, prop, pa,
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"phy_sgmii3");
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break;
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case FM2_DTSEC1:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy41");
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break;
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case FM2_DTSEC2:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy42");
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break;
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case FM2_DTSEC3:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy43");
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break;
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case FM2_DTSEC4:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy44");
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break;
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case FM2_DTSEC6:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy32");
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break;
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case FM2_DTSEC9:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy34");
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else
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fdt_set_phy_handle(blob, prop, pa,
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"phy_sgmii12");
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break;
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case FM2_DTSEC10:
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if (qsgmiiphy_fix[port])
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fdt_set_phy_handle(blob, prop, pa,
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"sgmii_phy33");
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else
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fdt_set_phy_handle(blob, prop, pa,
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"phy_sgmii11");
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break;
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default:
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break;
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}
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} else if (interface == PHY_INTERFACE_MODE_XGMII &&
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((prtcl2 == 55) || (prtcl2 == 57))) {
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/*
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* if the 10G is XFI, check hwconfig to see what is the
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* media type, there are two types, fiber or copper,
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* fix the dtb accordingly.
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*/
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int media_type = 0;
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struct fixed_link f_link;
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char lane_mode[20] = {"10GBASE-KR"};
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char buf[32] = "serdes-2,";
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int off;
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switch (port) {
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case FM1_10GEC1:
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if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
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media_type = 1;
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fdt_set_phy_handle(blob, prop, pa,
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"phy_xfi1");
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sprintf(buf, "%s%s%s", buf, "lane-a,",
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(char *)lane_mode);
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}
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break;
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case FM1_10GEC2:
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if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
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media_type = 1;
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fdt_set_phy_handle(blob, prop, pa,
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"phy_xfi2");
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sprintf(buf, "%s%s%s", buf, "lane-b,",
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(char *)lane_mode);
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}
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break;
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case FM2_10GEC1:
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if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
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media_type = 1;
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fdt_set_phy_handle(blob, prop, pa,
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"phy_xfi3");
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sprintf(buf, "%s%s%s", buf, "lane-d,",
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(char *)lane_mode);
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}
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break;
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case FM2_10GEC2:
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if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
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media_type = 1;
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fdt_set_phy_handle(blob, prop, pa,
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"phy_xfi4");
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sprintf(buf, "%s%s%s", buf, "lane-c,",
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(char *)lane_mode);
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}
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break;
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default:
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return;
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}
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if (!media_type) {
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/* fixed-link is used for XFI fiber cable */
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fdt_delprop(blob, offset, "phy-handle");
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f_link.phy_id = port;
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f_link.duplex = 1;
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f_link.link_speed = 10000;
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f_link.pause = 0;
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f_link.asym_pause = 0;
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fdt_setprop(blob, offset, "fixed-link", &f_link,
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sizeof(f_link));
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} else {
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/* set property for copper cable */
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off = fdt_node_offset_by_compat_reg(blob,
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"fsl,fman-memac-mdio", pa + 0x1000);
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fdt_setprop_string(blob, off, "lane-instance", buf);
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}
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int i;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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switch (mdio_mux[i]) {
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case EMI1_SLOT1:
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fdt_status_okay_by_alias(fdt, "emi1_slot1");
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break;
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case EMI1_SLOT2:
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fdt_status_okay_by_alias(fdt, "emi1_slot2");
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break;
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case EMI1_SLOT3:
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fdt_status_okay_by_alias(fdt, "emi1_slot3");
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break;
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case EMI1_SLOT4:
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fdt_status_okay_by_alias(fdt, "emi1_slot4");
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break;
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default:
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break;
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}
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break;
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case PHY_INTERFACE_MODE_XGMII:
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/* check if it's XFI interface for 10g */
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if ((prtcl2 == 55) || (prtcl2 == 57)) {
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if (i == FM1_10GEC1 && hwconfig_sub(
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"fsl_10gkr_copper", "fm1_10g1"))
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fdt_status_okay_by_alias(
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fdt, "xfi_pcs_mdio1");
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if (i == FM1_10GEC2 && hwconfig_sub(
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"fsl_10gkr_copper", "fm1_10g2"))
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fdt_status_okay_by_alias(
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fdt, "xfi_pcs_mdio2");
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if (i == FM2_10GEC1 && hwconfig_sub(
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"fsl_10gkr_copper", "fm2_10g1"))
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fdt_status_okay_by_alias(
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fdt, "xfi_pcs_mdio3");
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if (i == FM2_10GEC2 && hwconfig_sub(
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"fsl_10gkr_copper", "fm2_10g2"))
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fdt_status_okay_by_alias(
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fdt, "xfi_pcs_mdio4");
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break;
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}
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switch (i) {
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case FM1_10GEC1:
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fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
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break;
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case FM1_10GEC2:
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fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
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break;
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case FM2_10GEC1:
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fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
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break;
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case FM2_10GEC2:
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fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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}
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static void initialize_qsgmiiphy_fix(void)
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{
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int i;
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unsigned short reg;
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for (i = 1; i <= 4; i++) {
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/*
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* Try to read if a SGMII card is used, we do it slot by slot.
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* if a SGMII PHY address is valid on a slot, then we mark
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* all ports on the slot, then fix the PHY address for the
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* marked port when doing dtb fixup.
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*/
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if (miiphy_read(mdio_names[i],
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SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
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debug("Slot%d PHY ID register 2 read failed\n", i);
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continue;
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}
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debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
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if (reg == 0xFFFF) {
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/* No physical device present at this address */
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continue;
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}
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switch (i) {
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case 1:
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qsgmiiphy_fix[FM1_DTSEC5] = 1;
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qsgmiiphy_fix[FM1_DTSEC6] = 1;
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qsgmiiphy_fix[FM1_DTSEC9] = 1;
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qsgmiiphy_fix[FM1_DTSEC10] = 1;
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slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
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slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
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slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
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slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
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break;
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case 2:
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qsgmiiphy_fix[FM1_DTSEC1] = 1;
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qsgmiiphy_fix[FM1_DTSEC2] = 1;
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qsgmiiphy_fix[FM1_DTSEC3] = 1;
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qsgmiiphy_fix[FM1_DTSEC4] = 1;
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slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
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slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
|
|
break;
|
|
case 3:
|
|
qsgmiiphy_fix[FM2_DTSEC5] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC6] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC9] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC10] = 1;
|
|
slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
|
|
break;
|
|
case 4:
|
|
qsgmiiphy_fix[FM2_DTSEC1] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC2] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC3] = 1;
|
|
qsgmiiphy_fix[FM2_DTSEC4] = 1;
|
|
slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
|
|
slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
#if defined(CONFIG_FMAN_ENET)
|
|
int i, idx, lane, slot, interface;
|
|
struct memac_mdio_info dtsec_mdio_info;
|
|
struct memac_mdio_info tgec_mdio_info;
|
|
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
u32 srds_prtcl_s1, srds_prtcl_s2;
|
|
|
|
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
|
|
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
|
|
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
|
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
|
|
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
|
|
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
|
|
|
/* Initialize the mdio_mux array so we can recognize empty elements */
|
|
for (i = 0; i < NUM_FM_PORTS; i++)
|
|
mdio_mux[i] = EMI_NONE;
|
|
|
|
dtsec_mdio_info.regs =
|
|
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
|
|
|
|
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
|
|
|
|
/* Register the 1G MDIO bus */
|
|
fm_memac_mdio_init(bis, &dtsec_mdio_info);
|
|
|
|
tgec_mdio_info.regs =
|
|
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
|
|
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
|
|
|
|
/* Register the 10G MDIO bus */
|
|
fm_memac_mdio_init(bis, &tgec_mdio_info);
|
|
|
|
/* Register the muxing front-ends to the MDIO buses */
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
|
|
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
|
|
t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
|
|
|
|
initialize_qsgmiiphy_fix();
|
|
|
|
switch (srds_prtcl_s1) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
/* XAUI/HiGig in Slot1 and Slot2 */
|
|
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
|
|
break;
|
|
case 27:
|
|
case 28:
|
|
case 35:
|
|
case 36:
|
|
/* SGMII in Slot1 and Slot2 */
|
|
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
|
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
|
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
|
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
|
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
|
|
fm_info_set_phy_address(FM1_DTSEC9,
|
|
slot_qsgmii_phyaddr[1][3]);
|
|
fm_info_set_phy_address(FM1_DTSEC10,
|
|
slot_qsgmii_phyaddr[1][2]);
|
|
}
|
|
break;
|
|
case 37:
|
|
case 38:
|
|
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
|
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
|
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
|
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
|
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
|
|
fm_info_set_phy_address(FM1_DTSEC9,
|
|
slot_qsgmii_phyaddr[1][2]);
|
|
fm_info_set_phy_address(FM1_DTSEC10,
|
|
slot_qsgmii_phyaddr[1][3]);
|
|
}
|
|
break;
|
|
case 39:
|
|
case 40:
|
|
case 45:
|
|
case 46:
|
|
case 47:
|
|
case 48:
|
|
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
|
if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
|
|
fm_info_set_phy_address(FM1_DTSEC10,
|
|
slot_qsgmii_phyaddr[1][2]);
|
|
fm_info_set_phy_address(FM1_DTSEC9,
|
|
slot_qsgmii_phyaddr[1][3]);
|
|
}
|
|
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
|
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
|
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
|
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
|
break;
|
|
default:
|
|
puts("Invalid SerDes1 protocol for T4240QDS\n");
|
|
break;
|
|
}
|
|
|
|
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
|
idx = i - FM1_DTSEC1;
|
|
interface = fm_info_get_enet_if(i);
|
|
switch (interface) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
if (interface == PHY_INTERFACE_MODE_QSGMII) {
|
|
if (idx <= 3)
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
QSGMII_FM1_A);
|
|
else
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
QSGMII_FM1_B);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm1[lane];
|
|
debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
} else {
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_FM1_DTSEC1 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm1[lane];
|
|
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
}
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
switch (slot) {
|
|
case 1:
|
|
mdio_mux[i] = EMI1_SLOT1;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 2:
|
|
mdio_mux[i] = EMI1_SLOT2;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
};
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/* FM1 DTSEC5 routes to RGMII with EC2 */
|
|
debug("FM1@DTSEC%u is RGMII at address %u\n",
|
|
idx + 1, 2);
|
|
if (i == FM1_DTSEC5)
|
|
fm_info_set_phy_address(i, 2);
|
|
mdio_mux[i] = EMI1_RGMII;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
|
|
idx = i - FM1_10GEC1;
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_XGMII:
|
|
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
|
|
/* A fake PHY address to make U-Boot happy */
|
|
fm_info_set_phy_address(i, i);
|
|
} else {
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
XAUI_FM1_MAC9 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm1[lane];
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
}
|
|
mdio_mux[i] = EMI2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if (CONFIG_SYS_NUM_FMAN == 2)
|
|
switch (srds_prtcl_s2) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
/* XAUI/HiGig in Slot3 and Slot4 */
|
|
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
|
|
break;
|
|
case 6:
|
|
case 7:
|
|
case 12:
|
|
case 13:
|
|
case 14:
|
|
case 15:
|
|
case 16:
|
|
case 21:
|
|
case 22:
|
|
case 23:
|
|
case 24:
|
|
case 25:
|
|
case 26:
|
|
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
|
|
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
break;
|
|
case 27:
|
|
case 28:
|
|
case 35:
|
|
case 36:
|
|
/* SGMII in Slot3 and Slot4 */
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
|
|
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
|
|
break;
|
|
case 37:
|
|
case 38:
|
|
/* QSGMII in Slot3 and Slot4 */
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
|
|
break;
|
|
case 39:
|
|
case 40:
|
|
case 45:
|
|
case 46:
|
|
case 47:
|
|
case 48:
|
|
/* SGMII in Slot3 */
|
|
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
|
|
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
|
|
/* QSGMII in Slot4 */
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
break;
|
|
case 49:
|
|
case 50:
|
|
case 51:
|
|
case 52:
|
|
case 53:
|
|
case 54:
|
|
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
break;
|
|
case 55:
|
|
case 57:
|
|
/* XFI in Slot3, SGMII in Slot4 */
|
|
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
|
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
|
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
|
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
|
break;
|
|
default:
|
|
puts("Invalid SerDes2 protocol for T4240QDS\n");
|
|
break;
|
|
}
|
|
|
|
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
|
|
idx = i - FM2_DTSEC1;
|
|
interface = fm_info_get_enet_if(i);
|
|
switch (interface) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
if (interface == PHY_INTERFACE_MODE_QSGMII) {
|
|
if (idx <= 3)
|
|
lane = serdes_get_first_lane(FSL_SRDS_2,
|
|
QSGMII_FM2_A);
|
|
else
|
|
lane = serdes_get_first_lane(FSL_SRDS_2,
|
|
QSGMII_FM2_B);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm2[lane];
|
|
debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
} else {
|
|
lane = serdes_get_first_lane(FSL_SRDS_2,
|
|
SGMII_FM2_DTSEC1 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm2[lane];
|
|
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
}
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
switch (slot) {
|
|
case 3:
|
|
mdio_mux[i] = EMI1_SLOT3;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 4:
|
|
mdio_mux[i] = EMI1_SLOT4;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
};
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/*
|
|
* If DTSEC5 is RGMII, then it's routed via via EC1 to
|
|
* the first on-board RGMII port. If DTSEC6 is RGMII,
|
|
* then it's routed via via EC2 to the second on-board
|
|
* RGMII port.
|
|
*/
|
|
debug("FM2@DTSEC%u is RGMII at address %u\n",
|
|
idx + 1, i == FM2_DTSEC5 ? 1 : 2);
|
|
fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
|
|
mdio_mux[i] = EMI1_RGMII;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
|
|
idx = i - FM2_10GEC1;
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_XGMII:
|
|
if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
|
|
/* A fake PHY address to make U-Boot happy */
|
|
fm_info_set_phy_address(i, i);
|
|
} else {
|
|
lane = serdes_get_first_lane(FSL_SRDS_2,
|
|
XAUI_FM2_MAC9 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot_fsm2[lane];
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
}
|
|
mdio_mux[i] = EMI2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif /* CONFIG_SYS_NUM_FMAN */
|
|
|
|
cpu_eth_init(bis);
|
|
#endif /* CONFIG_FMAN_ENET */
|
|
|
|
return pci_eth_init(bis);
|
|
}
|