mirror of
https://github.com/brain-hackers/u-boot-brain
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![Prabhakar Kushwaha](/assets/img/avatar_default.png)
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
225 lines
5.8 KiB
C
225 lines
5.8 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <environment.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
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{
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int timeout = 1000;
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out_be32(ptr, value);
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while (in_be32(ptr) & bits) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0)
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puts("Error: wait for clear timeout.\n");
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}
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int checkboard(void)
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{
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u8 in1;
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puts("Board: LS1012ARDB ");
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/* Initialize i2c early for Serial flash bank information */
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i2c_set_bus_num(0);
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if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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puts("Version");
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if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
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puts(": RevA");
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else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
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puts(": RevB");
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else
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puts(": unknown");
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printf(", boot from QSPI");
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if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
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puts(": emu\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
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puts(": bank1\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
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puts(": bank2\n");
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else
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puts("unknown\n");
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return 0;
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}
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void mmdc_init(void)
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{
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struct mmdc_p_regs *mmdc =
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(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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/* configure timing parms */
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out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
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out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
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out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
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out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
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/* other parms */
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out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
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out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
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out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
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out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
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/* out of reset delays */
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out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
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/* physical parms */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
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out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
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/* Enable MMDC */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
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/* dram init sequence: update MRs */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
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CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
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/* dram init sequence: ZQCL */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
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CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
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FORCE_ZQ_AUTO_CALIBRATION);
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/* Calibrations now: wr lvl */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
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CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
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set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
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mdelay(1);
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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mdelay(1);
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/* Calibrations now: Read DQS gating calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
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set_wait_for_bits_clear(&mmdc->mpdgctrl0,
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AUTO_RD_DQS_GATING_CALIBRATION_EN,
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AUTO_RD_DQS_GATING_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* Calibrations now: Read calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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set_wait_for_bits_clear(&mmdc->mprddlhwctl,
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AUTO_RD_CALIBRATION_EN,
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AUTO_RD_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* PD, SR */
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out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
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out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
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/* refresh scheme */
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set_wait_for_bits_clear(&mmdc->mdref,
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CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
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START_REFRESH);
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/* disable CON_REQ */
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out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
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}
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int dram_init(void)
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{
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mmdc_init();
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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