mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
177 lines
4.0 KiB
C
177 lines
4.0 KiB
C
/*
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* multiverse.h
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*
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* VME driver for Multiverse
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*
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* Author : Sangmoon Kim
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* dogoil@etinsys.com
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*
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* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MULTIVERSE_H__
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#define __MULTIVERSE_H__
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#define VME_A32_MSTR_BUS 0x90000000
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#define VME_A32_MSTR_SIZE 0x01000000
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#define VME_A32_SLV_SIZE 0x01000000
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#define VME_A32_SLV_BUS 0x90000000
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#define VME_A24_SLV_BUS 0x00000000
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#define VME_A16_SLV_BUS 0x00000000
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#define VME_A32_SLV_LOCAL 0x00000000
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#define VME_A24_SLV_LOCAL 0x00000000
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#define VME_A16_SLV_LOCAL 0x00000000
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#define A32_SLV_WINDOW
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#undef A24_SLV_WINDOW
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#undef A16_SLV_WINDOW
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#undef REG_SLV_WINDOW
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/* PCI Registers */
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#define P_IMG_CTRL0 0x100
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#define P_BA0 0x104
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#define P_AM0 0x108
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#define P_TA0 0x10C
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#define P_IMG_CTRL1 0x110
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#define P_BA1 0x114
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#define P_AM1 0x118
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#define P_TA1 0x11C
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#define P_IMG_CTRL2 0x120
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#define P_BA2 0x124
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#define P_AM2 0x128
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#define P_TA2 0x12C
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#define P_IMG_CTRL3 0x130
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#define P_BA3 0x134
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#define P_AM3 0x138
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#define P_TA3 0x13C
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#define P_IMG_CTRL4 0x140
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#define P_BA4 0x144
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#define P_AM4 0x148
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#define P_TA4 0x14C
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#define P_IMG_CTRL5 0x150
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#define P_BA5 0x154
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#define P_AM5 0x158
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#define P_TA5 0x15C
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#define P_ERR_CS 0x160
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#define P_ERR_ADDR 0x164
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#define P_ERR_DATA 0x168
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#define WB_CONF_SPC_BAR 0x180
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#define W_IMG_CTRL1 0x184
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#define W_BA1 0x188
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#define W_AM1 0x18C
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#define W_TA1 0x190
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#define W_IMG_CTRL2 0x194
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#define W_BA2 0x198
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#define W_AM2 0x19C
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#define W_TA2 0x1A0
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#define W_IMG_CTRL3 0x1A4
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#define W_BA3 0x1A8
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#define W_AM3 0x1AC
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#define W_TA3 0x1B0
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#define W_IMG_CTRL4 0x1B4
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#define W_BA4 0x1B8
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#define W_AM4 0x1BC
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#define W_TA4 0x1C0
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#define W_IMG_CTRL5 0x1C4
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#define W_BA5 0x1C8
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#define W_AM5 0x1CC
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#define W_TA5 0x1D0
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#define W_ERR_CS 0x1D4
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#define W_ERR_ADDR 0x1D8
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#define W_ERR_DATA 0x1DC
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#define CNF_ADDR 0x1E0
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#define CNF_DATA 0x1E4
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#define INT_ACK 0x1E8
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#define ICR 0x1EC
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#define ISR 0x1F0
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/* VME registers */
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#define VME_SLAVE32_AM 0x03
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#define VME_SLAVE24_AM 0x02
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#define VME_SLAVE16_AM 0x01
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#define VME_SLAVE_REG_AM 0x00
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#define VME_SLAVE32_A 0x07
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#define VME_SLAVE24_A 0x06
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#define VME_SLAVE16_A 0x05
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#define VME_SLAVE_REG_A 0x04
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#define VME_SLAVE32_MASK 0x0B
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#define VME_SLAVE24_MASK 0x0A
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#define VME_SLAVE16_MASK 0x09
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#define VME_SLAVE_REG_MASK 0x08
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#define VME_SLAVE32_EN 0x0F
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#define VME_SLAVE24_EN 0x0E
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#define VME_SLAVE16_EN 0x0D
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#define VME_SLAVE_REG_EN 0x0C
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#define VME_MASTER32_AM 0x13
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#define VME_MASTER24_AM 0x12
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#define VME_MASTER16_AM 0x11
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#define VME_MASTER_REG_AM 0x10
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#define VME_RMW_ADRS 0x14
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#define VME_MBOX 0x18
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#define VME_STATUS 0x1E
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#define VME_CTRL 0x1C
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#define VME_IRQ 0x20
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#define VME_INT_EN 0x21
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#define VME_INT 0x22
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#define VME_IRQ1_REG 0x24
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#define VME_IRQ2_REG 0x28
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#define VME_IRQ3_REG 0x2C
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#define VME_IRQ4_REG 0x30
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#define VME_IRQ5_REG 0x34
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#define VME_IRQ6_REG 0x38
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#define VME_IRQ7_REG 0x3C
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/* VME control register */
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#define VME_CTRL_BRDRST 0x01
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#define VME_CTRL_SYSRST 0x02
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#define VME_CTRL_RMW 0x04
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#define VME_CTRL_SHORT_D 0x08
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#define VME_CTRL_SYSFAIL 0x10
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#define VME_CTRL_VOWN 0x20
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#define VME_CTRL_A16_REG_MODE 0x40
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/* VME status register */
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#define VME_STATUS_SYSCON 0x01
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#define VME_STATUS_SYSFAIL 0x02
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#define VME_STATUS_ACFAIL 0x04
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#define VME_STATUS_SYSRST 0x08
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#define VME_STATUS_VOWN 0x10
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/* Interrupt types */
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#define LVL1 0x0002
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#define LVL2 0x0004
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#define LVL3 0x0008
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#define LVL4 0x0010
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#define LVL5 0x0020
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#define LVL6 0x0040
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#define LVL7 0x0080
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#define MULTIVERSE_INTI_INT 0x0100
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#define MULTIVERSE_WB_INT 0x0200
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#define MULTIVERSE_PCI_INT 0x0400
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/* interrupt acknowledge */
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#define VME_IACK1 0x04
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#define VME_IACK2 0x08
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#define VME_IACK3 0x0c
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#define VME_IACK4 0x10
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#define VME_IACK5 0x14
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#define VME_IACK6 0x18
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#define VME_IACK7 0x1c
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#endif /* __MULTIVERSE_H__ */
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