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https://github.com/brain-hackers/u-boot-brain
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1cd46ed2d3
The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
24 lines
596 B
C
24 lines
596 B
C
/*
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* Copyright (c) 2013 Xilinx Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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extern void zynq_slcr_lock(void);
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extern void zynq_slcr_unlock(void);
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extern void zynq_slcr_cpu_reset(void);
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extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk);
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extern void zynq_slcr_devcfg_disable(void);
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extern void zynq_slcr_devcfg_enable(void);
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extern u32 zynq_slcr_get_boot_mode(void);
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extern u32 zynq_slcr_get_idcode(void);
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extern void zynq_ddrc_init(void);
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/* Driver extern functions */
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extern int zynq_sdhci_init(u32 regbase);
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#endif /* _SYS_PROTO_H_ */
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