mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
7cb22f97ee
environment variable which can set to "100", "133", or "150". The CPU clock will be configured accordingly upon next reboot. Other values are ignored. In case of an invalid or undefined "cpuclk" value, the compile-time default CPU clock speed will be used. * Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory window that is used to access the UART registers by the Linux driver) * Patch by Reinhard Meyer, 20 Dec 2003: Fix clock calculation for the MPC5200 for higher clock frequencies (above 2**32 / 10 = 429.5 MHz).
411 lines
13 KiB
C
411 lines
13 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8240 1
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#define CONFIG_SANDPOINT 1
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#if 0
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#define USE_DINK32 1
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#else
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#undef USE_DINK32
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#endif
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):$(netdev):off panic=1\0" \
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"net_self=tftp $(kernel_addr) $(bootfile);" \
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"tftp $(ramdisk_addr) $(ramdisk);" \
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"run ramargs addip;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp $(kernel_addr) $(bootfile);" \
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"run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/SP8240/uImage\0" \
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"ramdisk=/tftpboot/SP8240/uRamdisk\0" \
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"kernel_addr=200000\0" \
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"ramdisk_addr=400000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_AUTOSCRIPT) | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_SDRAM | \
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CFG_CMD_EEPROM | \
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CFG_CMD_PCI )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_DRAM_SPEED 100 /* MHz */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP 1 /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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#define PCI_ENET1_IOADDR 0x81000000
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#define PCI_ENET1_MEMADDR 0x81000000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MAX_RAM_SIZE 0x10000000
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#define CFG_RESET_ADDRESS 0xFFF00100
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#if defined (USE_DINK32)
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#define CFG_MONITOR_LEN 0x00030000
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#define CFG_MONITOR_BASE 0x00090000
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#define CFG_RAMBOOT 1
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#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_INIT_RAM_END 0x10000
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#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#else
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#undef CFG_RAMBOOT
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#define CFG_MONITOR_LEN 0x00030000
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#define CFG_MONITOR_BASE TEXT_BASE
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/*#define CFG_GBL_DATA_SIZE 256*/
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#define CFG_GBL_DATA_SIZE 128
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#define CFG_INIT_RAM_ADDR 0x40000000
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#endif
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#define CFG_FLASH_BASE 0xFFF00000
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#if 0
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#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
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#else
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#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
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#endif
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
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#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
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#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
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#define CFG_EUMB_ADDR 0xFC000000
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#define CFG_ISA_MEM 0xFD000000
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#define CFG_ISA_IO 0xFE000000
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#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
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#define CFG_FLASH_RANGE_SIZE 0x01000000
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#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
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#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
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/*
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* select i2c support configuration
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*
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* Supported configurations are {none, software, hardware} drivers.
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* If the software driver is chosen, there are some additional
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* configuration items that the driver uses to drive the port pins.
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*/
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#ifdef CONFIG_SOFT_I2C
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#error "Soft I2C is not configured properly. Please review!"
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
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else iop->pdat &= ~0x00010000
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
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else iop->pdat &= ~0x00020000
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
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#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
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#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
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#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
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#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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/*
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* NS87308 Configuration
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*/
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#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
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#define CFG_NS87308_BADDR_10 1
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#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
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CFG_NS87308_UART2 | \
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CFG_NS87308_POWRMAN | \
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CFG_NS87308_RTC_APC )
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#undef CFG_NS87308_PS2MOD
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#define CFG_NS87308_CS0_BASE 0x0076
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#define CFG_NS87308_CS0_CONF 0x30
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#define CFG_NS87308_CS1_BASE 0x0075
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#define CFG_NS87308_CS1_CONF 0x30
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#define CFG_NS87308_CS2_BASE 0x0074
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#define CFG_NS87308_CS2_CONF 0x30
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/*
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK 1843200
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#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
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#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
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#define CFG_ROMNAL 7 /*rom/flash next access time */
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#define CFG_ROMFAL 11 /*rom/flash access time */
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#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
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/* the following are for SDRAM only*/
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#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
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#define CFG_REFREC 8 /* Refresh to activate interval */
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#define CFG_RDLAT 4 /* data latency from read command */
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#define CFG_PRETOACT 3 /* Precharge to activate interval */
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#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CFG_ACTORW 3 /* Activate to R/W */
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#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
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#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
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#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
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#define CFG_REGISTERD_TYPE_BUFFER 1
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/* memory bank settings*/
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/*
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* only bits 20-29 are actually used from these vales to set the
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* start/end address the upper two bits will be 0, and the lower 20
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* bits will be set to 0x00000 for a start address, or 0xfffff for an
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* end address
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*/
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#define CFG_BANK0_START 0x00000000
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#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
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#define CFG_BANK0_ENABLE 1
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#define CFG_BANK1_START 0x3ff00000
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#define CFG_BANK1_END 0x3fffffff
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#define CFG_BANK1_ENABLE 0
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#define CFG_BANK2_START 0x3ff00000
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#define CFG_BANK2_END 0x3fffffff
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#define CFG_BANK2_ENABLE 0
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#define CFG_BANK3_START 0x3ff00000
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#define CFG_BANK3_END 0x3fffffff
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#define CFG_BANK3_ENABLE 0
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#define CFG_BANK4_START 0x00000000
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#define CFG_BANK4_END 0x00000000
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#define CFG_BANK4_ENABLE 0
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#define CFG_BANK5_START 0x00000000
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#define CFG_BANK5_END 0x00000000
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#define CFG_BANK5_ENABLE 0
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#define CFG_BANK6_START 0x00000000
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#define CFG_BANK6_END 0x00000000
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#define CFG_BANK6_ENABLE 0
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#define CFG_BANK7_START 0x00000000
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#define CFG_BANK7_END 0x00000000
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#define CFG_BANK7_ENABLE 0
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/*
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* Memory bank enable bitmask, specifying which of the banks defined above
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are actually present. MSB is for bank #7, LSB is for bank #0.
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*/
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#define CFG_BANK_ENABLE 0x01
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#define CFG_ODCR 0xff /* configures line driver impedances, */
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/* see 8240 book for bit definitions */
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#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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/* SDRAM 0 - 256MB */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in DCACHE @ 1GB (no backing mem) */
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#if defined(USE_DINK32)
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#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
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#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
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#else
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#endif
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/* PCI memory */
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#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Flash, config addrs, etc */
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#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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#define CFG_DBAT3L CFG_IBAT3L
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#define CFG_DBAT3U CFG_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/* values according to the manual */
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ
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#undef NR_8259_INTS
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#define NR_8259_INTS 1
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#define CONFIG_DISK_SPINUP_TIME 1000000
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#endif /* __CONFIG_H */
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