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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
This change lays the groundwork for the BOOTFLAG_* flags being removed. This change has the small affect of delaying 100ms on PCI initialization after a warm boot as opposed to the optimal 1ms on some boards. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> included the mpc8308_p1m board. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
210 lines
5.5 KiB
C
210 lines
5.5 KiB
C
/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pci_region pci1_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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};
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#ifdef CONFIG_MPC83XX_PCI2
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static struct pci_region pci2_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI2_MEM_BASE,
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phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
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size: CONFIG_SYS_PCI2_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI2_IO_BASE,
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phys_start: CONFIG_SYS_PCI2_IO_PHYS,
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size: CONFIG_SYS_PCI2_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
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size: CONFIG_SYS_PCI2_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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};
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#endif
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#ifndef CONFIG_PCISLAVE
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void pib_init(void)
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{
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u8 val8, orig_i2c_bus;
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/*
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* Assign PIB PMC slot to desired PCI bus
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*/
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/* Switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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#if defined(PCI_64BIT)
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val8 = 0xf4; /* PMC2:PCI1/64-bit */
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#elif defined(PCI_ALL_PCI1)
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val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
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#elif defined(PCI_ONE_PCI1)
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val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
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#else
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val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
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#endif
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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#if defined(PCI_64BIT)
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printf("PCI1: 64-bit on PMC2\n");
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#elif defined(PCI_ALL_PCI1)
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printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
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#elif defined(PCI_ONE_PCI1)
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printf("PCI1: 32-bit on PMC1\n");
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printf("PCI2: 32-bit on PMC2, PMC3\n");
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#else
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printf("PCI1: 32-bit on PMC1, PMC2\n");
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printf("PCI2: 32-bit on PMC3\n");
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#endif
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/* Reset to original I2C bus */
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i2c_set_bus_num(orig_i2c_bus);
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}
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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#ifndef CONFIG_MPC83XX_PCI2
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struct pci_region *reg[] = { pci1_regions };
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#else
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struct pci_region *reg[] = { pci1_regions, pci2_regions };
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#endif
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/* initialize the PCA9555PW IO expander on the PIB board */
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pib_init();
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/* Enable all 8 PCI_CLK_OUTPUTS */
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clk->occr = 0xff000000;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
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udelay(2000);
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#ifndef CONFIG_MPC83XX_PCI2
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mpc83xx_pci_init(1, reg);
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#else
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mpc83xx_pci_init(2, reg);
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#endif
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}
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#else
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
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struct pci_region *reg[] = { pci1_regions };
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
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mpc83xx_pci_init(1, reg);
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/* Configure PCI Inbound Translation Windows (3 1MB windows) */
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pci_ctrl->pitar0 = 0x0;
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pci_ctrl->pibar0 = 0x0;
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pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
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pci_ctrl->pitar1 = 0x0;
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pci_ctrl->pibar1 = 0x0;
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pci_ctrl->piebar1 = 0x0;
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pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
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pci_ctrl->pitar2 = 0x0;
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pci_ctrl->pibar2 = 0x0;
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pci_ctrl->piebar2 = 0x0;
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pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
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/* Unlock the configuration bit */
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mpc83xx_pcislave_unlock(0);
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printf("PCI: Agent mode enabled\n");
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}
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#endif /* CONFIG_PCISLAVE */
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