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https://github.com/brain-hackers/u-boot-brain
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![Shengzhou Liu](/assets/img/avatar_default.png)
The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor
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* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the QIXIS of some Freescale reference boards.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "qixis.h"
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u8 qixis_read(unsigned int reg)
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{
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void *p = (void *)QIXIS_BASE;
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return in_8(p + reg);
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}
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void qixis_write(unsigned int reg, u8 value)
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{
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void *p = (void *)QIXIS_BASE;
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out_8(p + reg, value);
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}
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void qixis_reset(void)
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{
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QIXIS_WRITE(rst_ctl, 0x83);
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}
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void qixis_bank_reset(void)
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{
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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}
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/* Set the boot bank to the power-on default bank0 */
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void clear_altbank(void)
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{
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u8 reg;
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reg = QIXIS_READ(brdcfg[0]);
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reg = reg & ~QIXIS_LBMAP_MASK;
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QIXIS_WRITE(brdcfg[0], reg);
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}
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/* Set the boot bank to the alternate bank */
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void set_altbank(void)
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{
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u8 reg;
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reg = QIXIS_READ(brdcfg[0]);
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reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
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QIXIS_WRITE(brdcfg[0], reg);
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}
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#ifdef DEBUG
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static void qixis_dump_regs(void)
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{
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int i;
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printf("id = %02x\n", QIXIS_READ(id));
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printf("arch = %02x\n", QIXIS_READ(arch));
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printf("scver = %02x\n", QIXIS_READ(scver));
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printf("model = %02x\n", QIXIS_READ(model));
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printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
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printf("aux = %02x\n", QIXIS_READ(aux));
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for (i = 0; i < 16; i++)
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printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
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for (i = 0; i < 16; i++)
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printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
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printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
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QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
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printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
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QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
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printf("aux = %02x\n", QIXIS_READ(aux));
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printf("watch = %02x\n", QIXIS_READ(watch));
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printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
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printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
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printf("present = %02x\n", QIXIS_READ(present));
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printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
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printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
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printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
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printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
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printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
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}
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#endif
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int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i;
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if (argc <= 1) {
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clear_altbank();
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qixis_reset();
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} else if (strcmp(argv[1], "altbank") == 0) {
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set_altbank();
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qixis_bank_reset();
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} else if (strcmp(argv[1], "watchdog") == 0) {
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static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
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"1min", "2min", "4min", "8min"};
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u8 rcfg = QIXIS_READ(rcfg_ctl);
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if (argv[2] == NULL) {
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printf("qixis watchdog <watchdog_period>\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(period); i++) {
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if (strcmp(argv[2], period[i]) == 0) {
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/* disable watchdog */
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QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
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QIXIS_WRITE(watch, ((i<<2) - 1));
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QIXIS_WRITE(rcfg_ctl, rcfg);
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return 0;
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}
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}
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}
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#ifdef DEBUG
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else if (strcmp(argv[1], "dump") == 0) {
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qixis_dump_regs();
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return 0;
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}
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#endif
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else {
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printf("Invalid option: %s\n", argv[1]);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
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"Reset the board using the FPGA sequencer",
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"- hard reset to default bank\n"
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"qixis_reset altbank - reset to alternate bank\n"
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"qixis watchdog <watchdog_period> - set the watchdog period\n"
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" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
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#ifdef DEBUG
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"qixis_reset dump - display the QIXIS registers\n"
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#endif
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);
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