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1be1433b83
u-boot-brain/arch/arm/include
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Tom Rini 1be1433b83 OMAP3: Add optimal SDRC autorefresh control values 
This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks.  We switch to using this
to provide the default 165MHz value.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
..
asm OMAP3: Add optimal SDRC autorefresh control values 2011-12-06 23:59:38 +01:00