mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
139 lines
2.8 KiB
C
139 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2009
|
|
* Marvell Semiconductor <www.marvell.com>
|
|
* Written-by: Siddarth Gore <gores@marvell.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <miiphy.h>
|
|
#include <asm/mach-types.h>
|
|
#include <asm/arch/cpu.h>
|
|
#include <asm/arch/soc.h>
|
|
#include <asm/arch/mpp.h>
|
|
#include "guruplug.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
/*
|
|
* default gpio configuration
|
|
* There are maximum 64 gpios controlled through 2 sets of registers
|
|
* the below configuration configures mainly initial LED status
|
|
*/
|
|
mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
|
|
GURUPLUG_OE_VAL_HIGH,
|
|
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
|
|
|
|
/* Multi-Purpose Pins Functionality configuration */
|
|
static const u32 kwmpp_config[] = {
|
|
MPP0_NF_IO2,
|
|
MPP1_NF_IO3,
|
|
MPP2_NF_IO4,
|
|
MPP3_NF_IO5,
|
|
MPP4_NF_IO6,
|
|
MPP5_NF_IO7,
|
|
MPP6_SYSRST_OUTn,
|
|
MPP7_GPO, /* GPIO_RST */
|
|
MPP8_TW_SDA,
|
|
MPP9_TW_SCK,
|
|
MPP10_UART0_TXD,
|
|
MPP11_UART0_RXD,
|
|
MPP12_SD_CLK,
|
|
MPP13_SD_CMD,
|
|
MPP14_SD_D0,
|
|
MPP15_SD_D1,
|
|
MPP16_SD_D2,
|
|
MPP17_SD_D3,
|
|
MPP18_NF_IO0,
|
|
MPP19_NF_IO1,
|
|
MPP20_GE1_0,
|
|
MPP21_GE1_1,
|
|
MPP22_GE1_2,
|
|
MPP23_GE1_3,
|
|
MPP24_GE1_4,
|
|
MPP25_GE1_5,
|
|
MPP26_GE1_6,
|
|
MPP27_GE1_7,
|
|
MPP28_GE1_8,
|
|
MPP29_GE1_9,
|
|
MPP30_GE1_10,
|
|
MPP31_GE1_11,
|
|
MPP32_GE1_12,
|
|
MPP33_GE1_13,
|
|
MPP34_GE1_14,
|
|
MPP35_GE1_15,
|
|
MPP36_GPIO,
|
|
MPP37_GPIO,
|
|
MPP38_GPIO,
|
|
MPP39_GPIO,
|
|
MPP40_TDM_SPI_SCK,
|
|
MPP41_TDM_SPI_MISO,
|
|
MPP42_TDM_SPI_MOSI,
|
|
MPP43_GPIO,
|
|
MPP44_GPIO,
|
|
MPP45_GPIO,
|
|
MPP46_GPIO, /* M_RLED */
|
|
MPP47_GPIO, /* M_GLED */
|
|
MPP48_GPIO, /* B_RLED */
|
|
MPP49_GPIO, /* B_GLED */
|
|
0
|
|
};
|
|
kirkwood_mpp_conf(kwmpp_config, NULL);
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/*
|
|
* arch number of board
|
|
*/
|
|
gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
|
|
|
|
/* adress of boot parameters */
|
|
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_RESET_PHY_R
|
|
void mv_phy_88e1121_init(char *name)
|
|
{
|
|
u16 reg;
|
|
u16 devadr;
|
|
|
|
if (miiphy_set_current_dev(name))
|
|
return;
|
|
|
|
/* command to read PHY dev address */
|
|
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
|
printf("Err..%s could not read PHY dev address\n",
|
|
__FUNCTION__);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Enable RGMII delay on Tx and Rx for CPU port
|
|
* Ref: sec 4.7.2 of chip datasheet
|
|
*/
|
|
miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
|
|
miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
|
|
reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
|
|
miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
|
|
miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
|
|
|
|
/* reset the phy */
|
|
miiphy_reset(name, devadr);
|
|
|
|
printf("88E1121 Initialized on %s\n", name);
|
|
}
|
|
|
|
void reset_phy(void)
|
|
{
|
|
/* configure and initialize both PHY's */
|
|
mv_phy_88e1121_init("egiga0");
|
|
mv_phy_88e1121_init("egiga1");
|
|
}
|
|
#endif /* CONFIG_RESET_PHY_R */
|