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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
320 lines
7.5 KiB
C
320 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Multicore Navigator driver for TI Keystone 2 devices.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ti-common/keystone_nav.h>
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struct qm_config qm_memmap = {
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.stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
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.queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
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.mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS,
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.i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE,
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.proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
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.status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE,
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.mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE,
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.intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE,
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.desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
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.region_num = CONFIG_KSNAV_QM_REGION_NUM,
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.pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
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.pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
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.pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
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.qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM,
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};
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/*
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* We are going to use only one type of descriptors - host packet
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* descriptors. We staticaly allocate memory for them here
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*/
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struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
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static struct qm_config *qm_cfg;
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inline int num_of_desc_to_reg(int num_descr)
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{
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int j, num;
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for (j = 0, num = 32; j < 15; j++, num *= 2) {
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if (num_descr <= num)
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return j;
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}
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return 15;
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}
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int _qm_init(struct qm_config *cfg)
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{
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u32 j;
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qm_cfg = cfg;
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qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
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qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8 - 1;
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qm_cfg->mngr_cfg->link_ram_base1 = 0;
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qm_cfg->mngr_cfg->link_ram_size1 = 0;
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qm_cfg->mngr_cfg->link_ram_base2 = 0;
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qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
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qm_cfg->desc_mem[0].start_idx = 0;
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qm_cfg->desc_mem[0].desc_reg_size =
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(((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
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num_of_desc_to_reg(HDESC_NUM);
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memset(desc_pool, 0, sizeof(desc_pool));
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for (j = 0; j < HDESC_NUM; j++)
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qm_push(&desc_pool[j], qm_cfg->qpool_num);
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return QM_OK;
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}
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int qm_init(void)
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{
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return _qm_init(&qm_memmap);
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}
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void qm_close(void)
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{
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u32 j;
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queue_close(qm_cfg->qpool_num);
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qm_cfg->mngr_cfg->link_ram_base0 = 0;
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qm_cfg->mngr_cfg->link_ram_size0 = 0;
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qm_cfg->mngr_cfg->link_ram_base1 = 0;
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qm_cfg->mngr_cfg->link_ram_size1 = 0;
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qm_cfg->mngr_cfg->link_ram_base2 = 0;
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for (j = 0; j < qm_cfg->region_num; j++) {
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qm_cfg->desc_mem[j].base_addr = 0;
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qm_cfg->desc_mem[j].start_idx = 0;
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qm_cfg->desc_mem[j].desc_reg_size = 0;
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}
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qm_cfg = NULL;
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}
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void qm_push(struct qm_host_desc *hd, u32 qnum)
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{
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u32 regd;
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cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
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regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
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writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
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}
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void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
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void *buff_ptr, u32 buff_len)
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{
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hd->orig_buff_len = buff_len;
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hd->buff_len = buff_len;
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hd->orig_buff_ptr = (u32)buff_ptr;
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hd->buff_ptr = (u32)buff_ptr;
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qm_push(hd, qnum);
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}
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struct qm_host_desc *qm_pop(u32 qnum)
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{
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u32 uhd;
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uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
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if (uhd)
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cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
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return (struct qm_host_desc *)uhd;
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}
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struct qm_host_desc *qm_pop_from_free_pool(void)
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{
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return qm_pop(qm_cfg->qpool_num);
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}
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void queue_close(u32 qnum)
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{
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struct qm_host_desc *hd;
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while ((hd = qm_pop(qnum)))
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;
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}
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/**
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* DMA API
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*/
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static int ksnav_rx_disable(struct pktdma_cfg *pktdma)
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{
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u32 j, v, k;
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for (j = 0; j < pktdma->rx_ch_num; j++) {
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v = readl(&pktdma->rx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a);
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for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
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udelay(100);
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v = readl(&pktdma->rx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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}
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/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
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}
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/* Clear all of the flow registers */
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for (j = 0; j < pktdma->rx_flow_num; j++) {
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writel(0, &pktdma->rx_flows[j].control);
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writel(0, &pktdma->rx_flows[j].tags);
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writel(0, &pktdma->rx_flows[j].tag_sel);
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writel(0, &pktdma->rx_flows[j].fdq_sel[0]);
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writel(0, &pktdma->rx_flows[j].fdq_sel[1]);
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writel(0, &pktdma->rx_flows[j].thresh[0]);
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writel(0, &pktdma->rx_flows[j].thresh[1]);
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writel(0, &pktdma->rx_flows[j].thresh[2]);
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}
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return QM_OK;
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}
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static int ksnav_tx_disable(struct pktdma_cfg *pktdma)
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{
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u32 j, v, k;
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for (j = 0; j < pktdma->tx_ch_num; j++) {
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v = readl(&pktdma->tx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a);
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for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
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udelay(100);
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v = readl(&pktdma->tx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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}
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/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
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}
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return QM_OK;
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}
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int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers)
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{
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u32 j, v;
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struct qm_host_desc *hd;
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u8 *rx_ptr;
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if (pktdma == NULL || rx_buffers == NULL ||
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rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
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return QM_ERR;
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pktdma->rx_flow = rx_buffers->rx_flow;
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/* init rx queue */
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rx_ptr = rx_buffers->buff_ptr;
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for (j = 0; j < rx_buffers->num_buffs; j++) {
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hd = qm_pop(qm_cfg->qpool_num);
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if (hd == NULL)
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return QM_ERR;
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qm_buff_push(hd, pktdma->rx_free_q,
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rx_ptr, rx_buffers->buff_len);
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rx_ptr += rx_buffers->buff_len;
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}
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ksnav_rx_disable(pktdma);
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/* configure rx channels */
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v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q);
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writel(v, &pktdma->rx_flows[pktdma->rx_flow].control);
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writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags);
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writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel);
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v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0,
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pktdma->rx_free_q);
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writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]);
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writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]);
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writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]);
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writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]);
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writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]);
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for (j = 0; j < pktdma->rx_ch_num; j++)
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writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a);
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/* configure tx channels */
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/* Disable loopback in the tx direction */
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writel(0, &pktdma->global->emulation_control);
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/* Set QM base address, only for K2x devices */
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writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
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/* Enable all channels. The current state isn't important */
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for (j = 0; j < pktdma->tx_ch_num; j++) {
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writel(0, &pktdma->tx_ch[j].cfg_b);
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writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a);
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}
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return QM_OK;
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}
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int ksnav_close(struct pktdma_cfg *pktdma)
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{
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if (!pktdma)
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return QM_ERR;
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ksnav_tx_disable(pktdma);
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ksnav_rx_disable(pktdma);
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queue_close(pktdma->rx_free_q);
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queue_close(pktdma->rx_rcv_q);
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queue_close(pktdma->tx_snd_q);
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return QM_OK;
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}
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int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
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{
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struct qm_host_desc *hd;
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hd = qm_pop(qm_cfg->qpool_num);
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if (hd == NULL)
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return QM_ERR;
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hd->desc_info = num_bytes;
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hd->swinfo[2] = swinfo2;
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hd->packet_info = qm_cfg->qpool_num;
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qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes);
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return QM_OK;
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}
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void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes)
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{
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struct qm_host_desc *hd;
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hd = qm_pop(pktdma->rx_rcv_q);
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if (!hd)
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return NULL;
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*pkt = (u32 *)hd->buff_ptr;
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*num_bytes = hd->desc_info & 0x3fffff;
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return hd;
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}
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void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd)
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{
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struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
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_hd->buff_len = _hd->orig_buff_len;
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_hd->buff_ptr = _hd->orig_buff_ptr;
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qm_push(_hd, pktdma->rx_free_q);
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}
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