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90bcc3d38d
The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.
This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2t
This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
122 lines
2.1 KiB
C
122 lines
2.1 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR_TOPOLOGY_DEF_H
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#define _DDR_TOPOLOGY_DEF_H
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#include "ddr3_training_ip_def.h"
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#include "ddr3_topology_def.h"
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#if defined(CONFIG_ARMADA_38X)
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#include "ddr3_a38x.h"
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#endif
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/* bus width in bits */
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enum hws_bus_width {
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BUS_WIDTH_4,
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BUS_WIDTH_8,
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BUS_WIDTH_16,
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BUS_WIDTH_32
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};
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enum hws_temperature {
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HWS_TEMP_LOW,
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HWS_TEMP_NORMAL,
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HWS_TEMP_HIGH
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};
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enum hws_mem_size {
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MEM_512M,
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MEM_1G,
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MEM_2G,
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MEM_4G,
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MEM_8G,
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MEM_SIZE_LAST
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};
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enum hws_timing {
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HWS_TIM_DEFAULT,
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HWS_TIM_1T,
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HWS_TIM_2T
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};
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struct bus_params {
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/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
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u8 cs_bitmask;
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/*
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* mirror enable/disable
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* (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
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*/
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int mirror_enable_bitmask;
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/* DQS Swap (polarity) - true if enable */
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int is_dqs_swap;
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/* CK swap (polarity) - true if enable */
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int is_ck_swap;
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};
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struct if_params {
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/* bus configuration */
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struct bus_params as_bus_params[MAX_BUS_NUM];
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/* Speed Bin Table */
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enum hws_speed_bin speed_bin_index;
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/* bus width of memory */
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enum hws_bus_width bus_width;
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/* Bus memory size (MBit) */
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enum hws_mem_size memory_size;
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/* The DDR frequency for each interfaces */
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enum hws_ddr_freq memory_freq;
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/*
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* delay CAS Write Latency
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* - 0 for using default value (jedec suggested)
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*/
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u8 cas_wl;
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/*
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* delay CAS Latency
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* - 0 for using default value (jedec suggested)
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*/
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u8 cas_l;
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/* operation temperature */
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enum hws_temperature interface_temp;
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/* 2T vs 1T mode (by default computed from number of CSs) */
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enum hws_timing timing;
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};
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struct hws_topology_map {
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/* Number of interfaces (default is 12) */
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u8 if_act_mask;
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/* Controller configuration per interface */
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struct if_params interface_params[MAX_INTERFACE_NUM];
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/* BUS per interface (default is 4) */
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u8 num_of_bus_per_interface;
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/* Bit mask for active buses */
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u8 bus_act_mask;
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};
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/* DDR3 training global configuration parameters */
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struct tune_train_params {
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u32 ck_delay;
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u32 ck_delay_16;
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u32 p_finger;
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u32 n_finger;
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u32 phy_reg3_val;
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};
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#endif /* _DDR_TOPOLOGY_DEF_H */
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