mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef fsl_mcdmafec_h
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#define fsl_mcdmafec_h
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/* Re-use of the definitions */
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#include <asm/fec.h>
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typedef struct fecdma {
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u32 rsvd0; /* 0x000 */
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u32 eir; /* 0x004 */
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u32 eimr; /* 0x008 */
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u32 rsvd1[6]; /* 0x00C - 0x023 */
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u32 ecr; /* 0x024 */
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u32 rsvd2[6]; /* 0x028 - 0x03F */
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u32 mmfr; /* 0x040 */
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u32 mscr; /* 0x044 */
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u32 rsvd3[7]; /* 0x048 - 0x063 */
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u32 mibc; /* 0x064 */
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u32 rsvd4[7]; /* 0x068 - 0x083 */
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u32 rcr; /* 0x084 */
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u32 rhr; /* 0x088 */
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u32 rsvd5[14]; /* 0x08C - 0x0C3 */
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u32 tcr; /* 0x0C4 */
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u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
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u32 palr; /* 0x0E4 */
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u32 paur; /* 0x0E8 */
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u32 opd; /* 0x0EC */
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u32 rsvd7[10]; /* 0x0F0 - 0x117 */
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u32 iaur; /* 0x118 */
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u32 ialr; /* 0x11C */
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u32 gaur; /* 0x120 */
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u32 galr; /* 0x124 */
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u32 rsvd8[7]; /* 0x128 - 0x143 */
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u32 tfwr; /* 0x144 */
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u32 rsvd9[14]; /* 0x148 - 0x17F */
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u32 fmc; /* 0x180 */
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u32 rfdr; /* 0x184 */
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u32 rfsr; /* 0x188 */
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u32 rfcr; /* 0x18C */
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u32 rlrfp; /* 0x190 */
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u32 rlwfp; /* 0x194 */
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u32 rfar; /* 0x198 */
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u32 rfrp; /* 0x19C */
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u32 rfwp; /* 0x1A0 */
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u32 tfdr; /* 0x1A4 */
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u32 tfsr; /* 0x1A8 */
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u32 tfcr; /* 0x1AC */
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u32 tlrfp; /* 0x1B0 */
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u32 tlwfp; /* 0x1B4 */
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u32 tfar; /* 0x1B8 */
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u32 tfrp; /* 0x1BC */
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u32 tfwp; /* 0x1C0 */
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u32 frst; /* 0x1C4 */
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u32 ctcwr; /* 0x1C8 */
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} fecdma_t;
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struct fec_info_dma {
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int index;
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u32 iobase;
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u32 pinmux;
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u32 miibase;
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int phy_addr;
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int dup_spd;
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char *phy_name;
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int phyname_init;
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cbd_t *rxbd; /* Rx BD */
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cbd_t *txbd; /* Tx BD */
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uint rxIdx;
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uint txIdx;
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char *txbuf;
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int initialized;
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struct fec_info_dma *next;
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u16 rxTask; /* DMA receive Task Number */
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u16 txTask; /* DMA Transmit Task Number */
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u16 rxPri; /* DMA Receive Priority */
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u16 txPri; /* DMA Transmit Priority */
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u16 rxInit; /* DMA Receive Initiator */
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u16 txInit; /* DMA Transmit Initiator */
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u16 usedTbdIdx; /* next transmit BD to clean */
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u16 cleanTbdNum; /* the number of available transmit BDs */
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};
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/* Bit definitions and macros for IEVENT */
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#define FEC_EIR_TXERR (0x00040000)
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#define FEC_EIR_RXERR (0x00020000)
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#undef FEC_EIR_CLEAR_ALL
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#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
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/* Bit definitions and macros for R_HASH */
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#define FEC_RHASH_FCE_DC (0x80000000)
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#define FEC_RHASH_MULTCAST (0x40000000)
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#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
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/* Bit definitions and macros for FEC_TFWR */
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#undef FEC_TFWR_X_WMRK
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#undef FEC_TFWR_X_WMRK_64
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#undef FEC_TFWR_X_WMRK_128
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#undef FEC_TFWR_X_WMRK_192
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#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
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#define FEC_TFWR_X_WMRK_64 (0x00)
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#define FEC_TFWR_X_WMRK_128 (0x01)
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#define FEC_TFWR_X_WMRK_192 (0x02)
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#define FEC_TFWR_X_WMRK_256 (0x03)
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#define FEC_TFWR_X_WMRK_320 (0x04)
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#define FEC_TFWR_X_WMRK_384 (0x05)
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#define FEC_TFWR_X_WMRK_448 (0x06)
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#define FEC_TFWR_X_WMRK_512 (0x07)
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#define FEC_TFWR_X_WMRK_576 (0x08)
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#define FEC_TFWR_X_WMRK_640 (0x09)
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#define FEC_TFWR_X_WMRK_704 (0x0A)
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#define FEC_TFWR_X_WMRK_768 (0x0B)
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#define FEC_TFWR_X_WMRK_832 (0x0C)
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#define FEC_TFWR_X_WMRK_896 (0x0D)
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#define FEC_TFWR_X_WMRK_960 (0x0E)
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#define FEC_TFWR_X_WMRK_1024 (0x0F)
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/* FIFO definitions */
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/* Bit definitions and macros for FSTAT */
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#define FIFO_STAT_IP (0x80000000)
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#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
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#define FIFO_STAT_FAE (0x00800000)
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#define FIFO_STAT_RXW (0x00400000)
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#define FIFO_STAT_UF (0x00200000)
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#define FIFO_STAT_OF (0x00100000)
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#define FIFO_STAT_FR (0x00080000)
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#define FIFO_STAT_FULL (0x00040000)
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#define FIFO_STAT_ALARM (0x00020000)
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#define FIFO_STAT_EMPTY (0x00010000)
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/* Bit definitions and macros for FCTRL */
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#define FIFO_CTRL_WCTL (0x40000000)
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#define FIFO_CTRL_WFR (0x20000000)
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#define FIFO_CTRL_FRAME (0x08000000)
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#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
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#define FIFO_CTRL_IPMASK (0x00800000)
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#define FIFO_CTRL_FAEMASK (0x00400000)
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#define FIFO_CTRL_RXWMASK (0x00200000)
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#define FIFO_CTRL_UFMASK (0x00100000)
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#define FIFO_CTRL_OFMASK (0x00080000)
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#endif /* fsl_mcdmafec_h */
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