mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
0dc0e846f3
This patch adds support for the Palm Treo 680 smartphone. A quick overview of u-boot implementation on the treo 680... The treo 680 has a Diskonchip G4 nand flash chip. This device has a 2k region that maps to the system bus at the reset vector in a NOR-like fashion so that it can be used as the boot device. The phone is shipped with this 2k region configured as write-protected (can't be modified) and programmed with an initial program loader (IPL). At power-up, this IPL loads the contents of two flash blocks to SDRAM and jumps to it. The capacity of the two blocks is not large enough to hold all of u-boot, so a u-boot SPL is used. To conserve flash space, these two blocks and the necessary number of subsequent blocks are programmed with a concatenated spl + u-boot image. That way, the IPL will also load a portion of u-boot proper, and when the spl runs, it relocates the portion of u-boot that the IPL has already loaded, and then resumes loading the remaining part of u-boot before jumping to it. The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think that having a writable environment was worth the cost of a flash block, although adding it would be straightforward. I abuse the CONFIG_EXTRA_ENV_SETTINGS option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV). Support for the LCD is included, but currently it is only useful for displaying the u-boot splash screen. But if u-boot is built without the usbtty console, it does display the auto-boot progress nicely. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
149 lines
3.7 KiB
C
149 lines
3.7 KiB
C
/*
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* Palm Treo 680 Support
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*
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* Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <serial.h>
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#include <nand.h>
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#include <malloc.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch-pxa/pxa.h>
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#include <asm/arch-pxa/regs-mmc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <u-boot/crc.h>
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#include <linux/mtd/docg4.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct nand_chip docg4_nand_chip;
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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/* IPL initializes SDRAM (we're already running from it) */
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#ifdef CONFIG_LCD
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void lcd_enable(void)
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{
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/*
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* Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
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* driver code. We need it as an output gpio.
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*/
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writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
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/* power-up and enable the lcd */
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writel(0x00400000, GPSR(86)); /* enable; drive high */
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writel(0x00002000, GPSR(77)); /* power; drive high */
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writel(0x02000000, GPCR(25)); /* enable_n; drive low */
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/* turn on LCD backlight and configure PWM for reasonable brightness */
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writel(0x00, PWM_CTRL0);
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writel(0x1b1, PWM_PERVAL0);
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writel(0xfd, PWM_PWDUTY0);
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writel(0x00000040, GPSR(38)); /* backlight power on */
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}
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#endif
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#ifdef CONFIG_MMC
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int board_mmc_init(bd_t *bis)
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{
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writel(1 << 10, GPSR(42)); /* power on */
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return pxa_mmc_register(0);
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}
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#endif
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void board_nand_init(void)
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{
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/* we have one 128M diskonchip G4 */
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struct mtd_info *mtd = &nand_info[0];
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struct nand_chip *nand = &docg4_nand_chip;
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if (docg4_nand_init(mtd, nand, 0))
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hang();
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}
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#ifdef CONFIG_SPL_BUILD
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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extern const void *_start, *_end; /* boundaries of spl in memory */
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/* size of spl; ipl loads this, and then a portion of u-boot */
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const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
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/* the flash offset of the blocks that are loaded by the spl */
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const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
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DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
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/* total number of bytes loaded by IPL */
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const size_t ipl_load_size =
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DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
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/* number of bytes of u-boot proper that was loaded by the IPL */
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const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
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/* number of remaining bytes of u-boot that the SPL must load */
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const size_t spl_load_size =
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CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
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/* memory address where we resume loading u-boot */
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void *const load_addr =
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(void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
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/*
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* Copy the portion of u-boot already read from flash by the IPL to its
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* correct load address.
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*/
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memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
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/*
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* Resume loading u-boot where the IPL left off.
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*/
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nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
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#ifdef CONFIG_NAND_ENV_DST
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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/*
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* Jump to U-Boot image
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*/
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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(*uboot)();
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}
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void board_init_f(ulong bootflag)
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{
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nand_boot();
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}
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#endif /* CONFIG_SPL_BUILD */
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