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https://github.com/brain-hackers/u-boot-brain
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
22 lines
502 B
C
22 lines
502 B
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MIPS_CACHE_H__
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#define __MIPS_CACHE_H__
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/*
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* The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
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* that as a default for aligning DMA buffers unless the board config has
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* specified another cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 128
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#endif
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#endif /* __MIPS_CACHE_H__ */
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