u-boot-brain/arch/arm/mach-imx/mx7
Bryan O'Donoghue 1ab1ffded4 imx: mx7: Add comment to describe OTP TESTER registers
The tester registers provide a unique chip-level identifier which
get_board_serial() returns in a "struct tag_serialnr".

This patch documents the properties of the registers; in summary.

31:0 OCOTP_TESTER0 (most significant)
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID

OCOTP_TESTER1 (least significant)
31:24
- The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
  ID
23:16
- The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
  ID
15:11
- The wafer number of the wafer on which the device was fabricated/SJC
  CHALLENGE/ Unique ID
10:0
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID

The 64 bits of data generate a unique serial number per-chip.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15 11:44:13 +02:00
..
clock_slice.c imx: reorganize IMX code as other SOCs 2017-07-12 10:17:44 +02:00
clock.c arm: imx: Rework i.MX specific commands to be excluded from SPL 2018-01-12 14:28:04 +01:00
ddr.c imx: mx7: DDR controller configuration for the i.MX7 architecture 2017-10-12 17:31:16 +02:00
Kconfig imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig 2018-01-08 17:33:06 +01:00
Makefile imx: mx7: DDR controller configuration for the i.MX7 architecture 2017-10-12 17:31:16 +02:00
psci-mx7.c imx: mx7: psci: add system power off support 2018-02-04 12:00:58 +01:00
psci.S imx: mx7: psci: add system power off support 2018-02-04 12:00:58 +01:00
soc.c imx: mx7: Add comment to describe OTP TESTER registers 2018-04-15 11:44:13 +02:00