mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#ifndef _DV_DDR2_DEFS_H_
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#define _DV_DDR2_DEFS_H_
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/*
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* DDR2 Memory Ctrl Register structure
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* See sprueh7d.pdf for more details.
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*/
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struct dv_ddr2_regs_ctrl {
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unsigned char rsvd0[4]; /* 0x00 */
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unsigned int sdrstat; /* 0x04 */
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unsigned int sdbcr; /* 0x08 */
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unsigned int sdrcr; /* 0x0C */
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unsigned int sdtimr; /* 0x10 */
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unsigned int sdtimr2; /* 0x14 */
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unsigned char rsvd1[4]; /* 0x18 */
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unsigned int sdbcr2; /* 0x1C */
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unsigned int pbbpr; /* 0x20 */
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unsigned char rsvd2[156]; /* 0x24 */
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unsigned int irr; /* 0xC0 */
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unsigned int imr; /* 0xC4 */
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unsigned int imsr; /* 0xC8 */
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unsigned int imcr; /* 0xCC */
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unsigned char rsvd3[20]; /* 0xD0 */
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unsigned int ddrphycr; /* 0xE4 */
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unsigned int ddrphycr2; /* 0xE8 */
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unsigned char rsvd4[4]; /* 0xEC */
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};
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#define DV_DDR_PHY_PWRDNEN 0x40
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#define DV_DDR_PHY_EXT_STRBEN 0x80
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#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
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#define DV_DDR_SDTMR1_RFC_SHIFT 25
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#define DV_DDR_SDTMR1_RP_SHIFT 22
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#define DV_DDR_SDTMR1_RCD_SHIFT 19
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#define DV_DDR_SDTMR1_WR_SHIFT 16
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#define DV_DDR_SDTMR1_RAS_SHIFT 11
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#define DV_DDR_SDTMR1_RC_SHIFT 6
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#define DV_DDR_SDTMR1_RRD_SHIFT 3
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#define DV_DDR_SDTMR1_WTR_SHIFT 0
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#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
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#define DV_DDR_SDTMR2_XP_SHIFT 25
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#define DV_DDR_SDTMR2_ODT_SHIFT 23
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#define DV_DDR_SDTMR2_XSNR_SHIFT 16
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#define DV_DDR_SDTMR2_XSRD_SHIFT 8
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#define DV_DDR_SDTMR2_RTP_SHIFT 5
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#define DV_DDR_SDTMR2_CKE_SHIFT 0
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#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
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#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
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#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
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#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
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#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
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#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
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#define DV_DDR_SDCR_DDR2EN_SHIFT 20
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#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
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#define DV_DDR_SDCR_DDREN_SHIFT 17
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#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
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#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
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#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
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#define DV_DDR_SDCR_CL_SHIFT 9
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#define DV_DDR_SDCR_IBANK_SHIFT 4
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#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
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#define DV_DDR_SDRCR_LPMODEN (1 << 31)
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#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
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#define DV_DDR_SRCR_LPMODEN_SHIFT 31
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#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
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#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
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#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
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#define dv_ddr2_regs_ctrl \
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((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
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#endif /* _DV_DDR2_DEFS_H_ */
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