mirror of
https://github.com/brain-hackers/u-boot-brain
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f605079041
Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
/* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
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return PHY_INTERFACE_MODE_XGMII;
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if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_RGMII) &&
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(!is_serdes_configured(QSGMII_FM1_A)))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_RGMII) &&
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(!is_serdes_configured(QSGMII_FM1_A)))
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return PHY_INTERFACE_MODE_RGMII;
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/* handle SGMII */
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
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+ port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII_2500;
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break;
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default:
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break;
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}
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/* handle QSGMII */
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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/* check lane A on SerDes1 */
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if (is_serdes_configured(QSGMII_FM1_A))
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return PHY_INTERFACE_MODE_QSGMII;
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break;
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default:
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break;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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