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https://github.com/brain-hackers/u-boot-brain
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1a6337b013
The i.MX31 has three SPI buses and each bus has several chip selects and the MC13783 chip can be connected to any of these. The current RTC driver for MC13783 is hardcoded for CSPI2/SS2. This patch makes make MC13783 SPI bus and chip select configurable via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
179 lines
5.5 KiB
C
179 lines
5.5 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the LogicPD i.MX31 Litekit board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/mx31-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_MX31 1 /* in a mx31 */
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#define CONFIG_MX31_HCLK_FREQ 26000000
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Temporarily disabled */
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#if 0
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_FIT 1
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#define CONFIG_FIT_VERBOSE 1
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#endif
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_MX31_UART 1
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#define CFG_MX31_UART1 1
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#define CONFIG_HARD_SPI 1
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#define CONFIG_MXC_SPI 1
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS0 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DATE
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.23.168
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#define CONFIG_SERVERIP 192.168.23.2
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
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"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
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#define CONFIG_DRIVER_SMC911X 1
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#define CONFIG_DRIVER_SMC911X_BASE (CS4_BASE + 0x00020000)
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#define CONFIG_DRIVER_SMC911X_32_BIT 1
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "uboot> "
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0 /* memtest works on */
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#define CFG_MEMTEST_END 0x10000
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0 /* default load address */
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#define CFG_HZ 32000
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#define CONFIG_CMDLINE_EDITING 1
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_FLASH_BASE CS0_BASE
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x001f0000)
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE (64 * 1024)
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#define CFG_ENV_SIZE (64 * 1024)
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
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/*
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* JFFS2 partitions
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*/
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#endif /* __CONFIG_H */
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