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![Tetsuyuki Kobayashi](/assets/img/avatar_default.png)
Add dummy member to struct sh73a0_rwdt in sh73a0.h. Without this, initializing watch dog timer goes wrong. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
290 lines
5.2 KiB
C
290 lines
5.2 KiB
C
#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
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#define __ASM_ARCH_RMOBILE_SH73A0_H
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/* Global Timer */
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#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
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#define MERAM_BASE (0xE5580000)
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/* GIC */
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#define GIC_BASE (0xF0000100)
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#define ICCICR GIC_BASE
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/* Secure control register */
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#define LIFEC_SEC_SRC (0xE6110008)
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/* RWDT */
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#define RWDT_BASE (0xE6020000)
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/* HPB Semaphore Control Registers */
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#define HPB_BASE (0xE6001010)
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/* Bus Semaphore Control Registers */
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#define HPBSCR_BASE (0xE6001600)
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/* SBSC1 */
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#define SBSC1_BASE (0xFE400000)
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#define SDMRA1A (SBSC1_BASE + 0x100000)
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#define SDMRA2A (SBSC1_BASE + 0x1C0000)
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#define SDMRA3A (SBSC1_BASE + 0x104000)
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/* SBSC2 */
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#define SBSC2_BASE (0xFB400000)
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#define SDMRA1B (SBSC2_BASE + 0x100000)
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#define SDMRA2B (SBSC2_BASE + 0x1C0000)
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#define SDMRA3B (SBSC2_BASE + 0x104000)
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/* CPG */
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#define CPG_BASE (0xE6150000)
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#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
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#define WUPCR (CPG_BASE + 0x1010)
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#define SRESCR (CPG_BASE + 0x1018)
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#define PCLKCR (CPG_BASE + 0x1020)
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/* SYSC */
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#define SYSC_BASE (0xE6180000)
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#define RESCNT2 (SYSC_BASE + 0x8020)
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/* BSC */
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#define BSC_BASE (0xFEC10000)
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/* SCIF */
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#define SCIF0_BASE (0xE6C40000)
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#define SCIF1_BASE (0xE6C50000)
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#define SCIF2_BASE (0xE6C60000)
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#define SCIF3_BASE (0xE6C70000)
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#define SCIF4_BASE (0xE6C80000)
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#define SCIF5_BASE (0xE6CB0000)
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#define SCIF6_BASE (0xE6CC0000)
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#define SCIF7_BASE (0xE6CD0000)
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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/* RWDT */
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struct sh73a0_rwdt {
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u16 rwtcnt0; /* 0x00 */
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u16 dummy0; /* 0x02 */
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u16 rwtcsra0; /* 0x04 */
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u16 dummy1; /* 0x06 */
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u16 rwtcsrb0; /* 0x08 */
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};
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/* HPB Semaphore Control Registers */
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struct sh73a0_hpb {
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u32 hpbctrl0;
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u32 hpbctrl1;
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u32 hpbctrl2;
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u32 cccr;
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u32 dummy0; /* 0x20 */
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u32 hpbctrl4;
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u32 hpbctrl5;
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u32 dummy1; /* 0x2C */
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u32 hpbctrl6;
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};
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/* Bus Semaphore Control Registers */
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struct sh73a0_hpb_bscr {
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u32 mpsrc; /* 0x00 */
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u32 mpacctl; /* 0x04 */
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u32 dummy0[6];
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u32 smgpiosrc; /* 0x20 */
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u32 smgpioerr;
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u32 smgpiotime;
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u32 smgpiocnt;
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u32 dummy1[4]; /* 0x30 .. 0x3C */
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u32 smcmt2src;
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u32 smcmt2err;
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u32 smcmt2time;
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u32 smcmt2cnt;
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u32 smcpgsrc;
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u32 smcpgerr;
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u32 smcpgtime;
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u32 smcpgcnt;
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u32 dummy2[4]; /* 0x60 - 0x6C */
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u32 smsyscsrc;
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u32 smsyscerr;
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u32 smsysctime;
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u32 smsysccnt;
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};
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/* SBSC */
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struct sh73a0_sbsc {
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u32 dummy0[2]; /* 0x00, 0x04 */
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u32 sdcr0;
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u32 sdcr1;
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u32 sdpcr;
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u32 dummy1; /* 0x14 */
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u32 sdcr0s;
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u32 sdcr1s;
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u32 rtcsr;
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u32 dummy2; /* 0x24 */
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u32 rtcor;
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u32 rtcorh;
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u32 rtcors;
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u32 rtcorsh;
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u32 dummy3[2]; /* 0x38, 0x3C */
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u32 sdwcrc0;
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u32 sdwcrc1;
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u32 sdwcr00;
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u32 sdwcr01;
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u32 sdwcr10;
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u32 sdwcr11;
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u32 sdpdcr0;
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u32 dummy4; /* 0x5C */
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u32 sdwcr2;
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u32 sdwcrc2;
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u32 zqccr;
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u32 dummy5[6]; /* 0x6C .. 0x80 */
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u32 sdmracr0;
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u32 dummy6; /* 0x88 */
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u32 sdmrtmpcr;
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u32 dummy7; /* 0x90 */
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u32 sdmrtmpmsk;
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u32 dummy8; /* 0x98 */
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u32 sdgencnt;
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u32 dphycnt0;
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u32 dphycnt1;
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u32 dphycnt2;
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u32 dummy9[2]; /* 0xAC .. 0xB0 */
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u32 sddrvcr0;
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u32 dummy10[14]; /* 0xB8 .. 0xEC */
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u32 dptdivcr0;
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u32 dptdivcr1;
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u32 dptdivcr2;
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u32 dummy11; /* 0xFC */
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u32 sdptcr0;
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u32 sdptcr1;
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u32 sdptcr2;
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u32 sdptcr3; /* 0x10C */
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u32 dummy12[145]; /* 0x110 .. 0x350 */
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u32 dllcnt0; /* 0x354 */
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u32 sbscmon0;
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};
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/* CPG */
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struct sh73a0_sbsc_cpg {
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u32 frqcra; /* 0x00 */
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u32 frqcrb;
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u32 vclkcr1;
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u32 vclkcr2;
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u32 zbckcr;
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u32 flckcr;
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u32 fsiackcr;
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u32 vclkcr3;
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u32 rtstbcr;
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u32 systbcr;
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u32 pll1cr;
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u32 pll2cr;
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u32 mstpsr0;
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u32 dummy0; /* 0x34 */
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u32 mstpsr1;
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u32 mstpsr5;
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u32 mstpsr2;
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u32 dummy1; /* 0x44 */
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u32 mstpsr3;
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u32 mstpsr4;
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u32 dummy2; /* 0x50 */
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u32 astat;
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u32 dvfscr0;
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u32 dvfscr1;
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u32 dsitckcr;
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u32 dsi0pckcr;
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u32 dsi1pckcr;
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u32 dsi0phycr;
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u32 dsi1phycr;
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u32 sd0ckcr;
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u32 sd1ckcr;
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u32 sd2ckcr;
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u32 subckcr;
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u32 spuackcr;
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u32 msuckcr;
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u32 hsickcr;
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u32 fsibckcr;
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u32 spuvckcr;
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u32 mfck1cr;
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u32 mfck2cr;
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u32 dummy3[8]; /* 0xA0 .. 0xBC */
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u32 ckscr;
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u32 dummy4; /* 0xC4 */
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u32 pll1stpcr;
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u32 mpmode;
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u32 pllecr;
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u32 dummy5; /* 0xD4 */
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u32 pll0cr;
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u32 pll3cr;
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u32 dummy6; /* 0xE0 */
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u32 frqcrd;
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u32 dummyi7; /* 0xE8 */
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u32 vrefcr;
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u32 pll0stpcr;
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u32 dummy8; /* 0xF4 */
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u32 pll2stpcr;
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u32 pll3stpcr;
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u32 dummy9[4]; /* 0x100 .. 0x10c */
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u32 rmstpcr0;
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u32 rmstpcr1;
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u32 rmstpcr2;
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u32 rmstpcr3;
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u32 rmstpcr4;
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u32 rmstpcr5;
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u32 dummy10[2]; /* 0x128 .. 0x12c */
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u32 smstpcr0;
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u32 smstpcr1;
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u32 smstpcr2;
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u32 smstpcr3;
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u32 smstpcr4;
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u32 smstpcr5;
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u32 dummy11[2]; /* 0x148 .. 0x14c */
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u32 cpgxxcs4;
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u32 dummy12[7]; /* 0x154 .. 0x16c */
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u32 dvfscr2;
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u32 dvfscr3;
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u32 dvfscr4;
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u32 dvfscr5; /* 0x17C */
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};
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/* CPG SRCR part OK */
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struct sh73a0_sbsc_cpg_srcr {
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u32 srcr0;
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u32 dummy0; /* 0xA4 */
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u32 srcr1;
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u32 dummy1; /* 0xAC */
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u32 srcr2;
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u32 dummy2; /* 0xB4 */
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u32 srcr3;
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u32 srcr4;
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u32 dummy3; /* 0xC0 */
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u32 srcr5;
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};
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/* BSC */
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struct sh73a0_bsc {
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u32 cmncr;
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u32 cs0bcr;
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u32 cs2bcr;
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u32 dummy0; /* 0x0C */
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u32 cs4bcr;
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u32 cs5abcr;
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u32 cs5bbcr;
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u32 cs6abcr;
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u32 cs6bbcr;
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u32 cs0wcr;
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u32 cs2wcr;
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u32 dummy1; /* 0x2C */
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u32 cs4wcr;
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u32 cs5awcr;
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u32 cs5bwcr;
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u32 cs6awcr;
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u32 cs6bwcr;
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u32 rbwtcnt;
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u32 busycr;
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u32 dummy2; /* 0x5c */
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u32 cs7abcr;
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u32 cs7awcr;
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u32 dummy3[2]; /* 0x68, 0x6C */
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u32 bromtimcr;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */
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